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The SSE version differences for fmin/fmax are more involved than I thought.

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- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2011-09-22 03:27:22 +00:00
parent e33ca9ce1f
commit 2c2ccbf108
1 changed files with 4 additions and 3 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
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@ -12568,9 +12568,10 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
// instructions match the semantics of the common C idiom x<y?x:y but not // instructions match the semantics of the common C idiom x<y?x:y but not
// x<=y?x:y, because of how they handle negative zero (which can be // x<=y?x:y, because of how they handle negative zero (which can be
// ignored in unsafe-math mode). // ignored in unsafe-math mode).
if (Subtarget->hasXMM() && if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) { (Subtarget->hasXMMInt() ||
(Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned Opcode = 0; unsigned Opcode = 0;