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Fix PR6165. The bug was that LHSKnownZero was being and'd with DemandedMask

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when it should have been and'd with LowBits.  Fix that and while there beef
up the logic in the case of a negative LHS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94745 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2010-01-28 17:22:42 +00:00
parent 21569cddc1
commit 2c47368a7d
2 changed files with 31 additions and 3 deletions
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15
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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@ -681,10 +681,19 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
LHSKnownZero, LHSKnownOne, Depth+1))
return I;
if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits))
LHSKnownZero |= ~LowBits;
// The low bits of LHS are unchanged by the srem.
KnownZero |= LHSKnownZero & LowBits;
KnownOne |= LHSKnownOne & LowBits;
KnownZero |= LHSKnownZero & DemandedMask;
// If LHS is non-negative or has all low bits zero, then the upper bits
// are all zero.
if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits))
KnownZero |= ~LowBits;
// If LHS is negative and not all low bits are zero, then the upper bits
// are all one.
if (LHSKnownOne[BitWidth-1] && ((LHSKnownOne & LowBits) != 0))
KnownOne |= ~LowBits;
assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
}

19
test/Transforms/InstCombine/2010-01-28-NegativeSRem.ll Normal file
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@ -0,0 +1,19 @@
; RUN: opt < %s -instcombine -S | FileCheck %s
; PR6165
define i32 @f() {
entry:
br label %BB1
BB1: ; preds = %BB1, %entry
; CHECK: BB1:
%x = phi i32 [ -29, %entry ], [ 0, %BB1 ] ; <i32> [#uses=2]
%rem = srem i32 %x, 2 ; <i32> [#uses=1]
%t = icmp eq i32 %rem, -1 ; <i1> [#uses=1]
br i1 %t, label %BB2, label %BB1
; CHECK-NOT: br i1 false
BB2: ; preds = %BB1
; CHECK: BB2:
ret i32 %x
}