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Provide Thumb2 encodings for sxtb and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119185 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -901,9 +901,9 @@ multiclass T2I_st<bits<2> opcod, string opc,
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/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
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/// register and one whose operand is a register rotated by 8/16/24.
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multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
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def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iEXTr,
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opc, ".w\t$dst, $src",
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[(set rGPR:$dst, (opnode rGPR:$src))]> {
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def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
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opc, ".w\t$Rd, $Rm",
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[(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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@ -912,24 +912,26 @@ multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iEXTr,
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opc, ".w\t$dst, $src, ror $rot",
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[(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> {
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def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
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opc, ".w\t$Rd, $Rm, ror $rot",
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[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = {?,?}; // rotate
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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}
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// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
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multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
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def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iEXTr,
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opc, "\t$dst, $src",
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[(set rGPR:$dst, (opnode rGPR:$src))]>,
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def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
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opc, "\t$Rd, $Rm",
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[(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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@ -939,9 +941,9 @@ multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iEXTr,
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opc, "\t$dst, $src, ror $rot",
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[(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>,
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def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
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opc, "\t$dst, $Rm, ror $rot",
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[(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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@ -949,15 +951,17 @@ multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = {?,?}; // rotate
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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}
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// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
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// supported yet.
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multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
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def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iEXTr,
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opc, "\t$dst, $src", []> {
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def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
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opc, "\t$Rd, $Rm", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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@ -966,24 +970,26 @@ multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iEXTr,
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opc, "\t$dst, $src, ror $rot", []> {
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def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
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opc, "\t$Rd, $Rm, ror $rot", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = {?,?}; // rotate
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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}
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/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
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/// register and one whose operand is a register rotated by 8/16/24.
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multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
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def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iEXTAr,
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opc, "\t$dst, $LHS, $RHS",
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[(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>,
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def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
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opc, "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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@ -992,25 +998,27 @@ multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
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IIC_iEXTAsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
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[(set rGPR:$dst, (opnode rGPR:$LHS,
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(rotr rGPR:$RHS, rot_imm:$rot)))]>,
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def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
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IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
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[(set rGPR:$Rd, (opnode rGPR:$Rn,
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(rotr rGPR:$Rm, rot_imm:$rot)))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = {?,?}; // rotate
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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}
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// DO variant - disassembly only, no pattern
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multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
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def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iEXTAr,
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opc, "\t$dst, $LHS, $RHS", []> {
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def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
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opc, "\t$Rd, $Rn, $Rm", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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@ -1018,14 +1026,16 @@ multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
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let Inst{7} = 1;
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let Inst{5-4} = 0b00; // rotate
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}
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def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
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IIC_iEXTAsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
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def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
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IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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let Inst{15-12} = 0b1111;
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let Inst{7} = 1;
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let Inst{5-4} = {?,?}; // rotate
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bits<2> rot;
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let Inst{5-4} = rot{1-0}; // rotate
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}
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}
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@ -32,3 +32,6 @@
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cmp.w r0, #1114112
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@ CHECK: cmp.w r0, r1, lsl #5 @ encoding: [0x41,0x1f,0xb0,0xeb]
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cmp.w r0, r1, lsl #5
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@ CHECK: sxtab r0, r1, r0 @ encoding: [0x80,0xf0,0x41,0xfa]
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sxtab r0, r1, r0 @ encoding: [0x80,0xf0,0x41,0xfa]
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