From 2c59435ca5ebb4b59ee63c5ceaa8a51b466812ef Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Sat, 29 Jan 2005 15:42:07 +0000 Subject: [PATCH] first step towards a correct and complete stack. also add some forms for things that were getting stuck in the nightly tester. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19914 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaISelPattern.cpp | 82 +++++++++++++++++++++++--- lib/Target/Alpha/AlphaInstrBuilder.h | 0 lib/Target/Alpha/AlphaInstrInfo.td | 4 +- lib/Target/Alpha/AlphaRegisterInfo.cpp | 4 +- 4 files changed, 78 insertions(+), 12 deletions(-) delete mode 100644 lib/Target/Alpha/AlphaInstrBuilder.h diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 58d6227eddf..ad492447735 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -294,6 +294,24 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result) default: Node->dump(); assert(0 && "Node not handled!\n"); + + case ISD::CopyFromReg: + { + // Make sure we generate both values. + if (Result != notIn) + ExprMap[N.getValue(1)] = notIn; // Generate the token + else + Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); + + SDOperand Chain = N.getOperand(0); + + Select(Chain); + unsigned r = dyn_cast(Node)->getReg(); + //std::cerr << "CopyFromReg " << Result << " = " << r << "\n"; + BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r); + return Result; + } + case ISD::LOAD: { // Make sure we generate both values. @@ -346,16 +364,57 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result) BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2); return Result; - case ISD::SINT_TO_FP: + case ISD::EXTLOAD: + //include a conversion sequence for float loads to double + if (Result != notIn) + ExprMap[N.getValue(1)] = notIn; // Generate the token + else + Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); + + Tmp2 = MakeReg(MVT::f32); + + if (ConstantPoolSDNode *CP = dyn_cast(N.getOperand(1))) + if (Node->getValueType(0) == MVT::f64) { + assert(cast(Node)->getExtraValueType() == MVT::f32 && + "Bad EXTLOAD!"); + BuildMI(BB, Alpha::LDS, 1, Tmp2).addConstantPoolIndex(CP->getIndex()); + BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp2); + return Result; + } + Select(Node->getOperand(0)); // chain + Tmp1 = SelectExpr(Node->getOperand(1)); + BuildMI(BB, Alpha::LDS, 1, Tmp2).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp2); + return Result; + + + //case ISD::UINT_TO_FP: + + case ISD::SINT_TO_FP: { assert (N.getOperand(0).getValueType() == MVT::i64 && "only quads can be loaded from"); Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register - Tmp2 = MakeReg(DestType); - //so these instructions are not supported on ev56 - Opc = DestType == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS; - BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1); - Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS; - BuildMI(BB, Opc, 1, Result).addReg(Tmp1); + + //The hard way: + // Spill the integer to memory and reload it from there. + unsigned Size = MVT::getSizeInBits(MVT::i64)/8; + MachineFunction *F = BB->getParent(); + int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size); + + //STL LDS + //STQ LDT + Opc = DestType == MVT::f64 ? Alpha::STQ : Alpha::STL; + BuildMI(BB, Opc, 2).addReg(Tmp1).addFrameIndex(FrameIdx); + Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS; + BuildMI(BB, Opc, 1, Result).addFrameIndex(FrameIdx); + + //The easy way: doesn't work +// //so these instructions are not supported on ev56 +// Opc = DestType == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS; +// BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1); +// Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS; +// BuildMI(BB, Opc, 1, Result).addReg(Tmp1); + return Result; } } @@ -400,9 +459,15 @@ unsigned ISel::SelectExpr(SDOperand N) { Node->dump(); assert(0 && "Node not handled!\n"); + case ISD::ConstantPool: + Tmp1 = cast(N)->getIndex(); + AlphaLowering.restoreGP(BB); + BuildMI(BB, Alpha::LOAD, 1, Result).addConstantPoolIndex(Tmp1); + return Result; + case ISD::FrameIndex: Tmp1 = cast(N)->getIndex(); - BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp1 * 8).addReg(Alpha::R30); + BuildMI(BB, Alpha::LDA, 2, Result).addFrameIndex(Tmp1); return Result; case ISD::EXTLOAD: @@ -770,6 +835,7 @@ unsigned ISel::SelectExpr(SDOperand N) { case ISD::XOR: case ISD::SHL: case ISD::SRL: + case ISD::SRA: case ISD::MUL: assert (DestType == MVT::i64 && "Only do arithmetic on i64s!"); if(N.getOperand(1).getOpcode() == ISD::Constant && diff --git a/lib/Target/Alpha/AlphaInstrBuilder.h b/lib/Target/Alpha/AlphaInstrBuilder.h deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index e9548b77dbf..d2130d37eb4 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -326,9 +326,9 @@ def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //In //CVTQL F-P 17.030 Convert quadword to longword def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating -//CVTST F-P 16.2AC Convert S_floating to T_floating +def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtst $RA,$RC">; //Convert S_floating to T_floating //CVTTQ F-P 16.0AF Convert T_floating to quadword -//CVTTS F-P 16.0AC Convert T_floating to S_floating +def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts $RA,$RC">; //Convert T_floating to S_floating //S_floating : IEEE Single //T_floating : IEEE Double diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index e2cb4b0ad50..cfa8e6f1812 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -50,7 +50,7 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, unsigned SrcReg, int FrameIdx) const { //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); - BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addImm(FrameIdx * 8).addReg(Alpha::R30); + BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx); // assert(0 && "TODO"); } @@ -60,7 +60,7 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, unsigned DestReg, int FrameIdx) const{ //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0, DestReg); - BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addImm(FrameIdx * 8).addReg(Alpha::R30); + BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx); // assert(0 && "TODO"); }