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ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -799,7 +799,7 @@ static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
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// BXJ: Rm
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// MSRi/MSRsysi: so_imm
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// SRSW/SRS: ldstm_mode:$amode mode_imm
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// RFEW/RFE: ldstm_mode:$amode Rn
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// RFE: Rn
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static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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@@ -858,19 +858,26 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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NumOpsAdded = 2;
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return true;
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}
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if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
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Opcode == ARM::RFEW || Opcode == ARM::RFE) {
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if (Opcode == ARM::SRSW || Opcode == ARM::SRS) {
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ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
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MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
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if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
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MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
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else
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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decodeRn(insn))));
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NumOpsAdded = 3;
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return true;
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}
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if (Opcode == ARM::RFEDA || Opcode == ARM::RFEDB ||
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Opcode == ARM::RFEIA || Opcode == ARM::RFEIB ||
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Opcode == ARM::RFEDA_UPD || Opcode == ARM::RFEDB_UPD ||
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Opcode == ARM::RFEIA_UPD || Opcode == ARM::RFEIB_UPD) {
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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decodeRn(insn))));
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NumOpsAdded = 1;
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return true;
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}
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assert((Opcode == ARM::Bcc || Opcode == ARM::BL || Opcode == ARM::BL_pred
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|| Opcode == ARM::SMC || Opcode == ARM::SVC) &&
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