diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c0e935df584..8418bb12b99 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -11420,7 +11420,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
     t3 = t2;
 
   MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
-  MIB.addReg(t3);
+  MIB.addReg(t1);
 
   MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
   for (int i=0; i <= lastAddrIndx; ++i)
diff --git a/test/CodeGen/X86/atomic_op.ll b/test/CodeGen/X86/atomic_op.ll
index c8cb78e34ee..7c5abe2095c 100644
--- a/test/CodeGen/X86/atomic_op.ll
+++ b/test/CodeGen/X86/atomic_op.ll
@@ -107,10 +107,15 @@ entry:
         ; CHECK: cmpxchgl
   %17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic
 	store i32 %17, i32* %old
-        ; CHECK: andl
-        ; CHECK: notl
+        ; CHECK: movl	$1401, %[[R17mask:[a-z]*]]
+        ; CHECK: movl	[[R17atomic:.*]], %eax
+        ; CHECK: movl	%eax, %[[R17newval:[a-z]*]]
+        ; CHECK: andl	%[[R17mask]], %[[R17newval]]
+        ; CHECK: notl	%[[R17newval]]
         ; CHECK: lock
-        ; CHECK: cmpxchgl
+        ; CHECK: cmpxchgl	%[[R17newval]], [[R17atomic]]
+        ; CHECK: jne
+        ; CHECK: movl	%eax,
   %18 = atomicrmw nand i32* %val2, i32 1401 monotonic
   store i32 %18, i32* %old
         ; CHECK: andl