From 2c66edf434f136d78e4b311a5a4777d8ecc9635b Mon Sep 17 00:00:00 2001
From: Kevin Enderby <enderby@apple.com>
Date: Tue, 24 Apr 2012 15:55:00 +0000
Subject: [PATCH] Add missing test cases for ARM VLD4 (single 4-element
 structure to all lanes) instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155444 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/MC/Disassembler/ARM/neon.txt   | 24 ++++++++++++++++++++++++
 test/MC/Disassembler/ARM/neont2.txt | 25 +++++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt
index c5dbee3aa89..e7bc808ac94 100644
--- a/test/MC/Disassembler/ARM/neon.txt
+++ b/test/MC/Disassembler/ARM/neon.txt
@@ -1745,6 +1745,30 @@
 0x4f 0x1b 0xe0 0xf4
 # CHECK: vld4.32	{d17[0], d19[0], d21[0], d23[0]}, [r0]
 
+0x0f 0x0f 0xa4 0xf4
+# CHECK: vld4.8	{d0[], d1[], d2[], d3[]}, [r4]
+0x3f 0x0f 0xa4 0xf4
+# CHECK: vld4.8	{d0[], d2[], d4[], d6[]}, [r4, :32]
+0x1d 0x0f 0xa4 0xf4
+# CHECK: vld4.8	{d0[], d1[], d2[], d3[]}, [r4, :32]!
+0x35 0x0f 0xa4 0xf4
+# CHECK: vld4.8	{d0[], d2[], d4[], d6[]}, [r4, :32], r5
+0x4f 0x0f 0xa4 0xf4
+# CHECK: vld4.16	{d0[], d1[], d2[], d3[]}, [r4]
+0x7f 0x0f 0xa4 0xf4
+# CHECK: vld4.16	{d0[], d2[], d4[], d6[]}, [r4, :64]
+0x5d 0x0f 0xa4 0xf4
+# CHECK: vld4.16	{d0[], d1[], d2[], d3[]}, [r4, :64]!
+0x75 0x0f 0xa4 0xf4
+# CHECK: vld4.16	{d0[], d2[], d4[], d6[]}, [r4, :64], r5
+0x8f 0x0f 0xa4 0xf4
+# CHECK: vld4.32	{d0[], d1[], d2[], d3[]}, [r4]
+0xbf 0x0f 0xa4 0xf4
+# CHECK: vld4.32	{d0[], d2[], d4[], d6[]}, [r4, :64]
+0xdd 0x0f 0xa4 0xf4
+# CHECK: vld4.32	{d0[], d1[], d2[], d3[]}, [r4, :128]!
+0xf5 0x0f 0xa4 0xf4
+# CHECK: vld4.32	{d0[], d2[], d4[], d6[]}, [r4, :128], r5
 
 
 0x1f 0x07 0x40 0xf4
diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt
index 65cd2304149..3816fd7ec46 100644
--- a/test/MC/Disassembler/ARM/neont2.txt
+++ b/test/MC/Disassembler/ARM/neont2.txt
@@ -1486,6 +1486,31 @@
 0xe0 0xf9 0x4f 0x1b
 # CHECK: vld4.32	{d17[0], d19[0], d21[0], d23[0]}, [r0]
 
+0xa4 0xf9 0x0f 0x0f
+# CHECK: vld4.8	{d0[], d1[], d2[], d3[]}, [r4] 
+0xa4 0xf9 0x3f 0x0f
+# CHECK: vld4.8	{d0[], d2[], d4[], d6[]}, [r4, :32] 
+0xa4 0xf9 0x1d 0x0f
+# CHECK: vld4.8	{d0[], d1[], d2[], d3[]}, [r4, :32]! 
+0xa4 0xf9 0x35 0x0f
+# CHECK: vld4.8	{d0[], d2[], d4[], d6[]}, [r4, :32], r5 
+0xa4 0xf9 0x4f 0x0f
+# CHECK: vld4.16	{d0[], d1[], d2[], d3[]}, [r4] 
+0xa4 0xf9 0x7f 0x0f
+# CHECK: vld4.16	{d0[], d2[], d4[], d6[]}, [r4, :64] 
+0xa4 0xf9 0x5d 0x0f
+# CHECK: vld4.16	{d0[], d1[], d2[], d3[]}, [r4, :64]! 
+0xa4 0xf9 0x75 0x0f
+# CHECK: vld4.16	{d0[], d2[], d4[], d6[]}, [r4, :64], r5 
+0xa4 0xf9 0x8f 0x0f
+# CHECK: vld4.32	{d0[], d1[], d2[], d3[]}, [r4] 
+0xa4 0xf9 0xbf 0x0f
+# CHECK: vld4.32	{d0[], d2[], d4[], d6[]}, [r4, :64] 
+0xa4 0xf9 0xdd 0x0f
+# CHECK: vld4.32	{d0[], d1[], d2[], d3[]}, [r4, :128]! 
+0xa4 0xf9 0xf5 0x0f
+# CHECK: vld4.32	{d0[], d2[], d4[], d6[]}, [r4, :128], r5 
+
 0x40 0xf9 0x1f 0x07
 # CHECK: vst1.8	{d16}, [r0, :64]
 0x40 0xf9 0x4f 0x07