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Add AVX SSE4.1 round instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3948,6 +3948,38 @@ multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
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OpSize;
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}
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multiclass sse41_fp_unop_rm_avx<bits<8> opcps, bits<8> opcpd,
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string OpcodeStr> {
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// Intrinsic operation, reg.
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// Vector intrinsic operation, reg
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def PSr : SS4AIi8<opcps, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, OpSize;
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// Vector intrinsic operation, mem
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def PSm : Ii8<opcps, MRMSrcMem,
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(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, TA, OpSize, Requires<[HasSSE41]>;
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// Vector intrinsic operation, reg
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def PDr : SS4AIi8<opcpd, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, OpSize;
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// Vector intrinsic operation, mem
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def PDm : SS4AIi8<opcpd, MRMSrcMem,
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(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, OpSize;
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}
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multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
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string OpcodeStr,
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Intrinsic F32Int,
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@ -3999,7 +4031,51 @@ multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
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OpSize;
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}
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multiclass sse41_fp_binop_rm_avx<bits<8> opcss, bits<8> opcsd,
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string OpcodeStr> {
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// Intrinsic operation, reg.
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def SSr : SS4AIi8<opcss, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, OpSize;
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// Intrinsic operation, mem.
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def SSm : SS4AIi8<opcss, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, OpSize;
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// Intrinsic operation, reg.
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def SDr : SS4AIi8<opcsd, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, OpSize;
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// Intrinsic operation, mem.
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def SDm : SS4AIi8<opcsd, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, OpSize;
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}
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// FP round - roundss, roundps, roundsd, roundpd
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
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// Intrinsic form
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defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround",
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int_x86_sse41_round_ps, int_x86_sse41_round_pd>,
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VEX;
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defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
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int_x86_sse41_round_ss, int_x86_sse41_round_sd,
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0>, VEX_4V;
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// Instructions for the assembler
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defm VROUND : sse41_fp_unop_rm_avx<0x08, 0x09, "vround">, VEX;
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defm VROUND : sse41_fp_binop_rm_avx<0x0A, 0x0B, "vround">, VEX_4V;
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}
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defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
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int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
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let Constraints = "$src1 = $dst" in
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@ -11742,3 +11742,35 @@
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// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0x18,0x07]
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vpalignr $7, (%eax), %xmm2, %xmm3
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// CHECK: vroundsd $7, %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0xd9,0x07]
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vroundsd $7, %xmm1, %xmm2, %xmm3
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// CHECK: vroundsd $7, (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0x18,0x07]
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vroundsd $7, (%eax), %xmm2, %xmm3
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// CHECK: vroundss $7, %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0xd9,0x07]
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vroundss $7, %xmm1, %xmm2, %xmm3
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// CHECK: vroundss $7, (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0x18,0x07]
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vroundss $7, (%eax), %xmm2, %xmm3
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// CHECK: vroundpd $7, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0xda,0x07]
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vroundpd $7, %xmm2, %xmm3
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// CHECK: vroundpd $7, (%eax), %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0x18,0x07]
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vroundpd $7, (%eax), %xmm3
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// CHECK: vroundps $7, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0xda,0x07]
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vroundps $7, %xmm2, %xmm3
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// CHECK: vroundps $7, (%eax), %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0x18,0x07]
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vroundps $7, (%eax), %xmm3
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@ -1790,3 +1790,35 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc4,0x63,0x19,0x0f,0x28,0x07]
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vpalignr $7, (%rax), %xmm12, %xmm13
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// CHECK: vroundsd $7, %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x43,0x19,0x0b,0xeb,0x07]
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vroundsd $7, %xmm11, %xmm12, %xmm13
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// CHECK: vroundsd $7, (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x63,0x19,0x0b,0x28,0x07]
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vroundsd $7, (%rax), %xmm12, %xmm13
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// CHECK: vroundss $7, %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x43,0x19,0x0a,0xeb,0x07]
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vroundss $7, %xmm11, %xmm12, %xmm13
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// CHECK: vroundss $7, (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x63,0x19,0x0a,0x28,0x07]
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vroundss $7, (%rax), %xmm12, %xmm13
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// CHECK: vroundpd $7, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x43,0x79,0x09,0xec,0x07]
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vroundpd $7, %xmm12, %xmm13
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// CHECK: vroundpd $7, (%rax), %xmm13
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// CHECK: encoding: [0xc4,0x63,0x79,0x09,0x28,0x07]
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vroundpd $7, (%rax), %xmm13
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// CHECK: vroundps $7, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x43,0x79,0x08,0xec,0x07]
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vroundps $7, %xmm12, %xmm13
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// CHECK: vroundps $7, (%rax), %xmm13
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// CHECK: encoding: [0xc4,0x63,0x79,0x08,0x28,0x07]
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vroundps $7, (%rax), %xmm13
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