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Add AVX SSE4.1 round instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-07-03 00:37:44 +00:00
parent 273f7e4299
commit 2c70d4ad35
3 changed files with 140 additions and 0 deletions
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76
lib/Target/X86/X86InstrSSE.td
View File

@ -3948,6 +3948,38 @@ multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
OpSize;
}
multiclass sse41_fp_unop_rm_avx<bits<8> opcps, bits<8> opcpd,
string OpcodeStr> {
// Intrinsic operation, reg.
// Vector intrinsic operation, reg
def PSr : SS4AIi8<opcps, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, OpSize;
// Vector intrinsic operation, mem
def PSm : Ii8<opcps, MRMSrcMem,
(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, TA, OpSize, Requires<[HasSSE41]>;
// Vector intrinsic operation, reg
def PDr : SS4AIi8<opcpd, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, OpSize;
// Vector intrinsic operation, mem
def PDm : SS4AIi8<opcpd, MRMSrcMem,
(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, OpSize;
}
multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
string OpcodeStr,
Intrinsic F32Int,
@ -3999,7 +4031,51 @@ multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
OpSize;
}
multiclass sse41_fp_binop_rm_avx<bits<8> opcss, bits<8> opcsd,
string OpcodeStr> {
// Intrinsic operation, reg.
def SSr : SS4AIi8<opcss, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr,
"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, OpSize;
// Intrinsic operation, mem.
def SSm : SS4AIi8<opcss, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr,
"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, OpSize;
// Intrinsic operation, reg.
def SDr : SS4AIi8<opcsd, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr,
"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, OpSize;
// Intrinsic operation, mem.
def SDm : SS4AIi8<opcsd, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr,
"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, OpSize;
}
// FP round - roundss, roundps, roundsd, roundpd
let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
// Intrinsic form
defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround",
int_x86_sse41_round_ps, int_x86_sse41_round_pd>,
VEX;
defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
int_x86_sse41_round_ss, int_x86_sse41_round_sd,
0>, VEX_4V;
// Instructions for the assembler
defm VROUND : sse41_fp_unop_rm_avx<0x08, 0x09, "vround">, VEX;
defm VROUND : sse41_fp_binop_rm_avx<0x0A, 0x0B, "vround">, VEX_4V;
}
defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
let Constraints = "$src1 = $dst" in

32
test/MC/AsmParser/X86/x86_32-encoding.s
View File

@ -11742,3 +11742,35 @@
// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0x18,0x07]
vpalignr $7, (%eax), %xmm2, %xmm3
// CHECK: vroundsd $7, %xmm1, %xmm2, %xmm3
// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0xd9,0x07]
vroundsd $7, %xmm1, %xmm2, %xmm3
// CHECK: vroundsd $7, (%eax), %xmm2, %xmm3
// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0x18,0x07]
vroundsd $7, (%eax), %xmm2, %xmm3
// CHECK: vroundss $7, %xmm1, %xmm2, %xmm3
// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0xd9,0x07]
vroundss $7, %xmm1, %xmm2, %xmm3
// CHECK: vroundss $7, (%eax), %xmm2, %xmm3
// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0x18,0x07]
vroundss $7, (%eax), %xmm2, %xmm3
// CHECK: vroundpd $7, %xmm2, %xmm3
// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0xda,0x07]
vroundpd $7, %xmm2, %xmm3
// CHECK: vroundpd $7, (%eax), %xmm3
// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0x18,0x07]
vroundpd $7, (%eax), %xmm3
// CHECK: vroundps $7, %xmm2, %xmm3
// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0xda,0x07]
vroundps $7, %xmm2, %xmm3
// CHECK: vroundps $7, (%eax), %xmm3
// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0x18,0x07]
vroundps $7, (%eax), %xmm3

32
test/MC/AsmParser/X86/x86_64-encoding.s
View File

@ -1790,3 +1790,35 @@ pshufb CPI1_0(%rip), %xmm1
// CHECK: encoding: [0xc4,0x63,0x19,0x0f,0x28,0x07]
vpalignr $7, (%rax), %xmm12, %xmm13
// CHECK: vroundsd $7, %xmm11, %xmm12, %xmm13
// CHECK: encoding: [0xc4,0x43,0x19,0x0b,0xeb,0x07]
vroundsd $7, %xmm11, %xmm12, %xmm13
// CHECK: vroundsd $7, (%rax), %xmm12, %xmm13
// CHECK: encoding: [0xc4,0x63,0x19,0x0b,0x28,0x07]
vroundsd $7, (%rax), %xmm12, %xmm13
// CHECK: vroundss $7, %xmm11, %xmm12, %xmm13
// CHECK: encoding: [0xc4,0x43,0x19,0x0a,0xeb,0x07]
vroundss $7, %xmm11, %xmm12, %xmm13
// CHECK: vroundss $7, (%rax), %xmm12, %xmm13
// CHECK: encoding: [0xc4,0x63,0x19,0x0a,0x28,0x07]
vroundss $7, (%rax), %xmm12, %xmm13
// CHECK: vroundpd $7, %xmm12, %xmm13
// CHECK: encoding: [0xc4,0x43,0x79,0x09,0xec,0x07]
vroundpd $7, %xmm12, %xmm13
// CHECK: vroundpd $7, (%rax), %xmm13
// CHECK: encoding: [0xc4,0x63,0x79,0x09,0x28,0x07]
vroundpd $7, (%rax), %xmm13
// CHECK: vroundps $7, %xmm12, %xmm13
// CHECK: encoding: [0xc4,0x43,0x79,0x08,0xec,0x07]
vroundps $7, %xmm12, %xmm13
// CHECK: vroundps $7, (%rax), %xmm13
// CHECK: encoding: [0xc4,0x63,0x79,0x08,0x28,0x07]
vroundps $7, (%rax), %xmm13