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Move something that should be in the dag combiner from the legalizer to the
dag combiner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32431 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3034,6 +3034,20 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
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ST->getSrcValueOffset());
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}
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// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
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// FIXME: We shouldn't do this for TargetConstantFP's.
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if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
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SDOperand Tmp;
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if (CFP->getValueType(0) == MVT::f32) {
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Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
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} else {
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assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
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Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
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}
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return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
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ST->getSrcValueOffset());
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}
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if (CombinerAA) {
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// Walk up chain skipping non-aliasing memory nodes.
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SDOperand BetterChain = FindBetterChain(N, Chain);
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@ -1643,21 +1643,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
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if (!ST->isTruncatingStore()) {
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// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
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// FIXME: We shouldn't do this for TargetConstantFP's.
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// FIXME: move this to the DAG Combiner!
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if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(ST->getValue())) {
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if (CFP->getValueType(0) == MVT::f32) {
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Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
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} else {
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assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
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Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
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}
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Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
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ST->getSrcValueOffset());
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break;
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}
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switch (getTypeAction(ST->getStoredVT())) {
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case Legal: {
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Tmp3 = LegalizeOp(ST->getValue());
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@ -4825,6 +4810,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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ExpandOp(Node->getOperand(0), LL, LH);
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ExpandOp(Node->getOperand(1), RL, RH);
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unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
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// FIXME: Move this to the dag combiner.
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// MULHS implicitly sign extends its inputs. Check to see if ExpandOp
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// extended the sign bit of the low half through the upper half, and if so
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// emit a MULHS instead of the alternate sequence that is valid for any
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@ -4838,8 +4824,6 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
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LH.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
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// FIXME: Move this to the dag combiner.
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// Low part:
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Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
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// High part:
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