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[mips] Define pseudo instructions for spilling and copying accumulator

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registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-03-30 00:54:52 +00:00
parent f7cef7081b
commit 2cd7d3f9ce
3 changed files with 26 additions and 0 deletions
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8
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -66,6 +66,14 @@ let usesCustomInserter = 1, Predicates = [HasStdEnc],
defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
} }
/// Pseudo instructions for loading, storing and copying accumulator registers.
let isPseudo = 1 in {
defm LOAD_AC128 : LoadM<"load_ac128", ACRegs128>;
defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>;
}
def COPY_AC128 : PseudoSE<(outs ACRegs128:$dst), (ins ACRegs128:$src), []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction definition // Instruction definition
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

8
lib/Target/Mips/MipsDSPInstrInfo.td
View File

@ -1271,6 +1271,14 @@ def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary,
} }
/// Pseudo instructions for loading, storing and copying accumulator registers.
let isPseudo = 1 in {
defm LOAD_AC_DSP : LoadM<"load_ac_dsp", ACRegsDSP>;
defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSP>;
}
def COPY_AC_DSP : PseudoSE<(outs ACRegsDSP:$dst), (ins ACRegsDSP:$src), []>;
// Patterns. // Patterns.
class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
Pat<pattern, result>, Requires<[pred]>; Pat<pattern, result>, Requires<[pred]>;

10
lib/Target/Mips/MipsInstrInfo.td
View File

@ -436,6 +436,7 @@ class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
[(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMem"; let DecoderMethod = "DecodeMem";
let canFoldAsLoad = 1; let canFoldAsLoad = 1;
let mayLoad = 1;
} }
class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
@ -443,6 +444,7 @@ class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMem"; let DecoderMethod = "DecodeMem";
let mayStore = 1;
} }
multiclass LoadM<string opstr, RegisterClass RC, multiclass LoadM<string opstr, RegisterClass RC,
@ -794,6 +796,14 @@ let usesCustomInserter = 1 in {
defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
} }
/// Pseudo instructions for loading, storing and copying accumulator registers.
let isPseudo = 1 in {
defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>;
defm STORE_AC64 : StoreM<"store_ac64", ACRegs>;
}
def COPY_AC64 : PseudoSE<(outs ACRegs:$dst), (ins ACRegs:$src), []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction definition // Instruction definition
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//