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Teach FastISel to support register-immediate-immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127496 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -258,6 +258,14 @@ protected:
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unsigned Op0, bool Op0IsKill,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm);
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uint64_t Imm);
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/// FastEmitInst_rii - Emit a MachineInstr with one register operand
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/// and two immediate operands.
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///
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unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm1, uint64_t Imm2);
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/// FastEmitInst_rf - Emit a MachineInstr with two register operands
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/// FastEmitInst_rf - Emit a MachineInstr with two register operands
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/// and a result register in the given register class.
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/// and a result register in the given register class.
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///
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///
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@ -1099,6 +1099,29 @@ unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
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return ResultReg;
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return ResultReg;
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}
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}
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unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm1, uint64_t Imm2) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addImm(Imm1)
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.addImm(Imm2);
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else {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addImm(Imm1)
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.addImm(Imm2);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(II.ImplicitDefs[0]);
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}
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
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unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op0, bool Op0IsKill,
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