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Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60586 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-12-05 05:45:42 +00:00
parent 4c0d951780
commit 2ce7f2068f
5 changed files with 9 additions and 8 deletions
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4
include/llvm/CodeGen/MachineInstr.h
View File

@ -219,9 +219,9 @@ public:
/// none is found.
int findFirstPredOperandIdx() const;
/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
/// isRegReDefinedByTwoAddr - Given the index of a register def operand,
/// check if the register def is a re-definition due to two addr elimination.
bool isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const;
bool isRegReDefinedByTwoAddr(unsigned DefIdx) const;
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
///

2
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -426,7 +426,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// must be due to phi elimination or two addr elimination. If this is
// the result of two address elimination, then the vreg is one of the
// def-and-use register operand.
if (mi->isRegReDefinedByTwoAddr(interval.reg, MOIdx)) {
if (mi->isRegReDefinedByTwoAddr(MOIdx)) {
// If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we

7
lib/CodeGen/MachineInstr.cpp
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@ -646,13 +646,14 @@ int MachineInstr::findFirstPredOperandIdx() const {
return -1;
}
/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
/// isRegReDefinedByTwoAddr - Given the index of a register def operand,
/// check if the register def is a re-definition due to two addr elimination.
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{
assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!");
const TargetInstrDesc &TID = getDesc();
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.isUse() && MO.getReg() == Reg &&
if (MO.isReg() && MO.isUse() &&
TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
return true;
}

2
lib/CodeGen/PostRASchedulerList.cpp
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@ -478,7 +478,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
if (Reg == 0) continue;
if (!MO.isDef()) continue;
// Ignore two-addr defs.
if (MI->isRegReDefinedByTwoAddr(Reg, i)) continue;
if (MI->isRegReDefinedByTwoAddr(i)) continue;
DefIndices[Reg] = Count;
KillIndices[Reg] = -1;

2
lib/CodeGen/RegAllocLocal.cpp
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@ -609,7 +609,7 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
// Check if this is a two address instruction. If so, then
// the def does not kill the use.
if (last->second.first == I &&
I->isRegReDefinedByTwoAddr(MO.getReg(), i))
I->isRegReDefinedByTwoAddr(i))
continue;
MachineOperand& lastUD =