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R600: Code cleanup.
Use sign_extend_inreg and getZeroExtendInReg instead of using the bit operations they expand into. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203988 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -722,7 +722,6 @@ SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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unsigned Mask = (1 << Load->getMemoryVT().getSizeInBits()) - 1;
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SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
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DAG.getConstant(2, MVT::i32));
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SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
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@ -734,17 +733,16 @@ SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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DAG.getConstant(0x3, MVT::i32));
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SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
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DAG.getConstant(3, MVT::i32));
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Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
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Ret = DAG.getNode(ISD::AND, DL, MVT::i32, Ret,
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DAG.getConstant(Mask, MVT::i32));
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EVT MemEltVT = MemVT.getScalarType();
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if (ExtType == ISD::SEXTLOAD) {
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SDValue SExtShift = DAG.getConstant(
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VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
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Ret = DAG.getNode(ISD::SHL, DL, MVT::i32, Ret, SExtShift);
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Ret = DAG.getNode(ISD::SRA, DL, MVT::i32, Ret, SExtShift);
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SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
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}
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return Ret;
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return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
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}
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SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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@ -762,8 +760,9 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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return SplitVectorStore(Op, DAG);
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}
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EVT MemVT = Store->getMemoryVT();
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if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
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Store->getMemoryVT().bitsLT(MVT::i32)) {
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MemVT.bitsLT(MVT::i32)) {
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unsigned Mask = 0;
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if (Store->getMemoryVT() == MVT::i8) {
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Mask = 0xff;
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@ -781,10 +780,12 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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DAG.getConstant(3, MVT::i32));
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SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
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Store->getValue());
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SDValue MaskedValue = DAG.getNode(ISD::AND, DL, MVT::i32, SExtValue,
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DAG.getConstant(Mask, MVT::i32));
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SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
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SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
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MaskedValue, ShiftAmt);
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SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
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ShiftAmt);
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DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
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