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Give getPointerRegClass() a "kind" value so that targets can

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support multiple different pointer register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-07-29 20:31:52 +00:00
parent 0531d04d00
commit 2cfd52c507
11 changed files with 28 additions and 26 deletions
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5
include/llvm/Target/TargetRegisterInfo.h
View File

@ -514,8 +514,9 @@ public:
}
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
/// values.
virtual const TargetRegisterClass *getPointerRegClass() const {
/// values. If a target supports multiple different pointer register classes,
/// kind specifies which one is indicated.
virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
assert(0 && "Target didn't implement getPointerRegClass!");
return 0; // Must return a value in order to compile with VS 2005
}

9
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -1,4 +1,4 @@
//===- ARMBaseRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -224,8 +224,8 @@ BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const
return Reserved;
}
bool
ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
unsigned Reg) const {
switch (Reg) {
default: break;
case ARM::SP:
@ -243,7 +243,8 @@ ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) cons
return false;
}
const TargetRegisterClass *ARMBaseRegisterInfo::getPointerRegClass() const {
const TargetRegisterClass *
ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
return &ARM::GPRRegClass;
}

4
lib/Target/ARM/ARMBaseRegisterInfo.h
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@ -1,4 +1,4 @@
//===- ARMBaseRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
//===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -74,7 +74,7 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const;
const TargetRegisterClass *getPointerRegClass() const;
const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
getAllocationOrder(const TargetRegisterClass *RC,

4
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -219,8 +219,8 @@ SPURegisterInfo::getNumArgRegs()
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
const TargetRegisterClass * SPURegisterInfo::getPointerRegClass() const
{
const TargetRegisterClass *
SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
return &SPU::R32CRegClass;
}

3
lib/Target/CellSPU/SPURegisterInfo.h
View File

@ -43,7 +43,8 @@ namespace llvm {
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass() const;
virtual const TargetRegisterClass *
getPointerRegClass(unsigned Kind = 0) const;
//! Return the array of callee-saved registers
virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;

8
lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@ -46,7 +46,7 @@ MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CalleeSavedRegs;
}
const TargetRegisterClass* const*
const TargetRegisterClass *const *
MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
@ -59,8 +59,7 @@ MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
return CalleeSavedRegClasses;
}
BitVector
MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
// Mark 4 special registers as reserved.
@ -76,7 +75,8 @@ MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
const TargetRegisterClass* MSP430RegisterInfo::getPointerRegClass() const {
const TargetRegisterClass *
MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
return &MSP430::GR16RegClass;
}

2
lib/Target/MSP430/MSP430RegisterInfo.h
View File

@ -40,7 +40,7 @@ public:
getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
const TargetRegisterClass* getPointerRegClass() const;
const TargetRegisterClass* getPointerRegClass(unsigned Kind = 0) const;
bool hasFP(const MachineFunction &MF) const;
bool hasReservedCallFrame(MachineFunction &MF) const;

6
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -140,11 +140,11 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
const TargetRegisterClass *
PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
if (Subtarget.isPPC64())
return &PPC::G8RCRegClass;
else
return &PPC::GPRCRegClass;
return &PPC::GPRCRegClass;
}
const unsigned*

2
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -37,7 +37,7 @@ public:
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass() const;
virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const;
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;

9
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -245,12 +245,11 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
return 0;
}
const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
if (Subtarget->is64Bit())
const TargetRegisterClass *X86RegisterInfo::
getPointerRegClass(unsigned Kind) const {
if (TM.getSubtarget<X86Subtarget>().is64Bit())
return &X86::GR64RegClass;
else
return &X86::GR32RegClass;
return &X86::GR32RegClass;
}
const TargetRegisterClass *

2
lib/Target/X86/X86RegisterInfo.h
View File

@ -102,7 +102,7 @@ public:
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
/// values.
const TargetRegisterClass *getPointerRegClass() const;
const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
/// getCrossCopyRegClass - Returns a legal register class to copy a register
/// in the specified class to or from. Returns NULL if it is possible to copy