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Ensure bitcode encoding of instructions and their operands stays stable.

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This includes instructions with aggregate operands (insert/extract), instructions with vector operands (insert/extract/shuffle), binary arithmetic and bitwise instructions, conversion instructions and terminators.

Work was done by lama.saba@intel.com.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202262 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Kuperstein
2014-02-26 12:06:36 +00:00
parent 2e0d7a9337
commit 2d0eef4c7d
14 changed files with 583 additions and 0 deletions
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34
test/Bitcode/vectorInstructions.3.2.ll Normal file
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; RUN: llvm-dis < %s.bc| FileCheck %s
; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
; The test checks that LLVM does not misread vector operations of
; older bitcode files.
define void @extractelement(<2 x i8> %x1){
entry:
; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0
%res1 = extractelement <2 x i8> %x1, i32 0
ret void
}
define void @insertelement(<2 x i8> %x1){
entry:
; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
%res1 = insertelement <2 x i8> %x1, i8 0, i32 0
ret void
}
define void @shufflevector(<2 x i8> %x1){
entry:
; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
%res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>
%res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>
ret void
}