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Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly

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flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.

This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17068 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2004-10-16 20:43:38 +00:00
parent 6e758aee74
commit 2d4c98d79b
2 changed files with 12 additions and 12 deletions
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18
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -2550,25 +2550,23 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
// Longs, as usual, are handled specially... // Longs, as usual, are handled specially...
if (Class == cLong) { if (Class == cLong) {
// If we have a constant shift, we can generate much more efficient code // If we have a constant shift, we can generate much more efficient code
// than otherwise... // than for a variable shift by using the rlwimi instruction.
//
if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) { if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
unsigned Amount = CUI->getValue(); unsigned Amount = CUI->getValue();
if (Amount < 32) { if (Amount < 32) {
unsigned TempReg = makeAnotherReg(ResultTy);
if (isLeftShift) { if (isLeftShift) {
// FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg)
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
.addImm(Amount).addImm(0).addImm(31-Amount); .addImm(Amount).addImm(0).addImm(31-Amount);
BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1) BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg).addReg(TempReg)
.addImm(Amount).addImm(32-Amount).addImm(31); .addReg(SrcReg+1).addImm(Amount).addImm(32-Amount).addImm(31);
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1) BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
.addImm(Amount).addImm(0).addImm(31-Amount); .addImm(Amount).addImm(0).addImm(31-Amount);
} else { } else {
// FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg+1)
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
.addImm(32-Amount).addImm(Amount).addImm(31); .addImm(32-Amount).addImm(Amount).addImm(31);
BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg) BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg)
.addImm(32-Amount).addImm(0).addImm(Amount-1); .addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1);
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg) BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
.addImm(32-Amount).addImm(Amount).addImm(31); .addImm(32-Amount).addImm(Amount).addImm(31);
} }

6
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -412,9 +412,11 @@ def FSUBS : AForm_2<59, 20, 0, 0, 0,
// M-Form instructions. rotate and mask instructions. // M-Form instructions. rotate and mask instructions.
// //
let isTwoAddress = 1 in {
def RLWIMI : MForm_2<20, 0, 0, 0, def RLWIMI : MForm_2<20, 0, 0, 0,
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
"rlwimi $rA, $rS, $SH, $MB, $ME">; u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
}
def RLWINM : MForm_2<21, 0, 0, 0, def RLWINM : MForm_2<21, 0, 0, 0,
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
"rlwinm $rA, $rS, $SH, $MB, $ME">; "rlwinm $rA, $rS, $SH, $MB, $ME">;