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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169848 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -595,14 +595,14 @@ public:
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/// getRegisterType - Return the type of registers that this ValueType will
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/// eventually require.
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EVT getRegisterType(MVT VT) const {
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MVT getRegisterType(MVT VT) const {
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assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
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return RegisterTypeForVT[VT.SimpleTy];
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}
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/// getRegisterType - Return the type of registers that this ValueType will
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/// eventually require.
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EVT getRegisterType(LLVMContext &Context, EVT VT) const {
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MVT getRegisterType(LLVMContext &Context, EVT VT) const {
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if (VT.isSimple()) {
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assert((unsigned)VT.getSimpleVT().SimpleTy <
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array_lengthof(RegisterTypeForVT));
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@ -613,7 +613,7 @@ public:
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unsigned NumIntermediates;
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(void)getVectorTypeBreakdown(Context, VT, VT1,
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NumIntermediates, RegisterVT);
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return RegisterVT;
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return RegisterVT.getSimpleVT();
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}
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if (VT.isInteger()) {
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return getRegisterType(Context, getTypeToTransformTo(Context, VT));
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@ -1931,7 +1931,7 @@ private:
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/// each ValueType the target supports natively.
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const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
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unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
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EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
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MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
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/// RepRegClassForVT - This indicates the "representative" register class to
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/// use for each ValueType the target supports natively. This information is
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@ -226,7 +226,7 @@ unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
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unsigned FirstReg = 0;
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT ValueVT = ValueVTs[Value];
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MVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT).getSimpleVT();
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MVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
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unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
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for (unsigned i = 0; i != NumRegs; ++i) {
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@ -321,7 +321,7 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
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// Do a (aligned) store to a stack slot, then copy from the stack slot
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// to the final destination using (unaligned) integer loads and stores.
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EVT StoredVT = ST->getMemoryVT();
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EVT RegVT =
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MVT RegVT =
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TLI.getRegisterType(*DAG.getContext(),
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EVT::getIntegerVT(*DAG.getContext(),
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StoredVT.getSizeInBits()));
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@ -447,7 +447,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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// Copy the value to a (aligned) stack slot using (unaligned) integer
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// loads and stores, then do a (aligned) load from the stack slot.
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EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
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MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
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unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
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unsigned RegBytes = RegVT.getSizeInBits() / 8;
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unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
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@ -703,7 +703,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
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EVT VT = N->getValueType(0);
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DebugLoc dl = N->getDebugLoc();
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EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
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MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
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unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
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// The argument is passed as NumRegs registers of type RegVT.
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@ -610,7 +610,7 @@ namespace {
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT ValueVT = ValueVTs[Value];
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unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
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EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
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MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
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for (unsigned i = 0; i != NumRegs; ++i)
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Regs.push_back(Reg + i);
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RegVTs.push_back(RegisterVT);
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@ -1238,7 +1238,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
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unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
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EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
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MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
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SmallVector<SDValue, 4> Parts(NumParts);
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getCopyToParts(DAG, getCurDebugLoc(),
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SDValue(RetOp.getNode(), RetOp.getResNo() + j),
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@ -6412,7 +6412,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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Flags.setNest();
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Flags.setOrigAlign(OriginalAlignment);
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EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
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MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
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unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
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SmallVector<SDValue, 4> Parts(NumParts);
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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@ -6447,11 +6447,11 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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ComputeValueVTs(*this, CLI.RetTy, RetTys);
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for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
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EVT VT = RetTys[I];
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EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
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MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
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unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
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for (unsigned i = 0; i != NumRegs; ++i) {
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ISD::InputArg MyFlags;
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MyFlags.VT = RegisterVT.getSimpleVT();
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MyFlags.VT = RegisterVT;
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MyFlags.Used = CLI.IsReturnValueUsed;
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if (CLI.RetSExt)
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MyFlags.Flags.setSExt();
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@ -6501,7 +6501,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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unsigned CurReg = 0;
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for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
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EVT VT = RetTys[I];
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EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
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MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
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unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
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ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
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@ -6591,7 +6591,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
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// or one register.
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ISD::ArgFlagsTy Flags;
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Flags.setSRet();
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EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
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MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
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ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
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Ins.push_back(RetArg);
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}
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@ -6637,7 +6637,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
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Flags.setNest();
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Flags.setOrigAlign(OriginalAlignment);
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EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
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MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
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unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
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for (unsigned i = 0; i != NumRegs; ++i) {
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ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
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@ -6684,7 +6684,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
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SmallVector<EVT, 1> ValueVTs;
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ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
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MVT VT = ValueVTs[0].getSimpleVT();
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MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT).getSimpleVT();
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MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
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ISD::NodeType AssertOp = ISD::DELETED_NODE;
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SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
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RegVT, VT, NULL, AssertOp);
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@ -6716,7 +6716,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
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for (unsigned Val = 0; Val != NumValues; ++Val) {
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EVT VT = ValueVTs[Val];
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EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
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MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
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unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
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if (!I->use_empty()) {
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@ -688,7 +688,7 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
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if (!isPowerOf2_32(NewVTSize))
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NewVTSize = NextPowerOf2(NewVTSize);
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EVT DestVT = TLI->getRegisterType(NewVT);
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MVT DestVT = TLI->getRegisterType(NewVT);
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RegisterVT = DestVT;
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if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
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return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
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@ -870,7 +870,7 @@ void TargetLowering::computeRegisterProperties() {
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NumRegistersForVT[i] =
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getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
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RegisterVT, this);
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RegisterTypeForVT[i] = RegisterVT;
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RegisterTypeForVT[i] = RegisterVT.getSimpleVT();
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MVT NVT = VT.getPow2VectorType();
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if (NVT == VT) {
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@ -1011,13 +1011,13 @@ void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
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// conventions. The frontend should mark functions whose return values
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// require promoting with signext or zeroext attributes.
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if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
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EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
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MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
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if (VT.bitsLT(MinVT))
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VT = MinVT;
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}
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unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
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EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
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MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
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// 'inreg' on function refers to return value
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ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
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@ -1909,11 +1909,11 @@ bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
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ComputeValueVTs(TLI, I->getType(), RetTys);
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for (unsigned i = 0, e = RetTys.size(); i != e; ++i) {
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EVT VT = RetTys[i];
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EVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT);
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MVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT);
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unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT);
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for (unsigned j = 0; j != NumRegs; ++j) {
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ISD::InputArg MyFlags;
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MyFlags.VT = RegisterVT.getSimpleVT();
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MyFlags.VT = RegisterVT;
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MyFlags.Used = !CS.getInstruction()->use_empty();
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if (CS.paramHasAttr(0, Attributes::SExt))
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MyFlags.Flags.setSExt();
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