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Fix PSHUF* and SHUF* jit code emission problems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26949 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -64,6 +64,8 @@ def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
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// SDI - SSE2 instructions with XD prefix.
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// PSI - SSE1 instructions with TB prefix.
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
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class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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@ -72,6 +74,14 @@ class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
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class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
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class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasSSE1]> {
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let Pattern = pattern;
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}
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class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
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let Pattern = pattern;
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}
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// Some 'special' instructions
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def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
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@ -671,33 +681,33 @@ def CMPPDrm : PDI<0xC2, MRMSrcMem,
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}
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// Shuffle and unpack instructions
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def PSHUFWrr : PSI<0x70, AddRegFrm,
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(ops VR64:$dst, VR64:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFWrm : PSI<0x70, MRMSrcMem,
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(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFDrr : PDI<0x70, AddRegFrm,
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(ops VR128:$dst, VR128:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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def PSHUFWrr : PSIi8<0x70, MRMDestReg,
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(ops VR64:$dst, VR64:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFWrm : PSIi8<0x70, MRMSrcMem,
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(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFDrr : PDIi8<0x70, MRMDestReg,
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(ops VR128:$dst, VR128:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (vector_shuffle (v4f32 VR128:$src1), (undef),
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PSHUFD_shuffle_mask:$src2))]>;
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def PSHUFDrm : PDI<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def SHUFPSrr : PSI<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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def SHUFPSrm : PSI<0xC6, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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def SHUFPDrr : PDI<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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def SHUFPDrm : PDI<0xC6, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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def SHUFPSrm : PSIi8<0xC6, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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def SHUFPDrm : PDIi8<0xC6, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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