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Implement Calls for V8. This would be completely autogenerated except for
a small bug in tblgen. When that is fixed, we can remove the ISD::Call case in Select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24830 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
dc464de9b0
commit
2db3ff66f1
@ -50,6 +50,7 @@ namespace V8ISD {
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namespace {
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class SparcV8TargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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public:
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SparcV8TargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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@ -154,7 +155,6 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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// TODO: FP
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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@ -278,6 +278,9 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// Store remaining ArgRegs to the stack if this is a varargs function.
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if (F.getFunctionType()->isVarArg()) {
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// Remember the vararg offset for the va_start implementation.
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VarArgsFrameOffset = ArgOffset;
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for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg, VReg);
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@ -325,8 +328,208 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, unsigned CC,
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bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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MachineFunction &MF = DAG.getMachineFunction();
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// Count the size of the outgoing arguments.
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unsigned ArgsSize = 0;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "Unknown value type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::f32:
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ArgsSize += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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ArgsSize += 8;
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break;
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}
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}
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if (ArgsSize > 4*6)
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ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
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else
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ArgsSize = 0;
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Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
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DAG.getConstant(ArgsSize, getPointerTy()));
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SDOperand StackPtr, NullSV;
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std::vector<SDOperand> Stores;
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std::vector<SDOperand> RegValuesToPass;
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unsigned ArgOffset = 68;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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SDOperand Val = Args[i].first;
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MVT::ValueType ObjectVT = Val.getValueType();
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SDOperand ValToStore;
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unsigned ObjSize;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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// Promote the integer to 32-bits. If the input type is signed, use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
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else
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Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
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// FALL THROUGH
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case MVT::i32:
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ObjSize = 4;
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if (RegValuesToPass.size() >= 6) {
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ValToStore = Val;
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} else {
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RegValuesToPass.push_back(Val);
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}
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break;
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case MVT::f32:
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ObjSize = 4;
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if (RegValuesToPass.size() >= 6) {
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ValToStore = Val;
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} else {
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// Convert this to a FP value in an int reg.
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int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand SV = DAG.getSrcValue(0);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Val, FIPtr, SV);
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Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV);
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RegValuesToPass.push_back(Val);
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}
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break;
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case MVT::f64: {
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ObjSize = 8;
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// If we can store this directly into the outgoing slot, do so. We can
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// do this when all ArgRegs are used and if the outgoing slot is aligned.
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if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
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ValToStore = Val;
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break;
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}
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// Otherwise, convert this to a FP value in int regs.
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int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand SV = DAG.getSrcValue(0);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Val, FIPtr, SV);
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Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV);
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}
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// FALL THROUGH
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case MVT::i64:
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ObjSize = 8;
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if (RegValuesToPass.size() >= 6) {
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ValToStore = Val; // Whole thing is passed in memory.
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break;
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}
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// Split the value into top and bottom part. Top part goes in a reg.
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
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DAG.getConstant(1, MVT::i32));
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
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DAG.getConstant(0, MVT::i32));
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RegValuesToPass.push_back(Hi);
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if (RegValuesToPass.size() >= 6) {
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ValToStore = Lo;
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} else {
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RegValuesToPass.push_back(Lo);
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}
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break;
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}
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if (ValToStore.Val) {
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if (!StackPtr.Val) {
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StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::SP, MVT::i32);
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NullSV = DAG.getSrcValue(NULL);
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}
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SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
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Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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ValToStore, PtrOff, NullSV));
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}
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ArgOffset += ObjSize;
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}
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// Emit all stores, make sure the occur before any copies into physregs.
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if (!Stores.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
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static const unsigned ArgRegs[] = {
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V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
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};
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// Build a sequence of copy-to-reg nodes chained together with token chain
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// and flag operands which copy the outgoing args into O[0-5].
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SDOperand InFlag;
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for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
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InFlag = Chain.getValue(1);
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}
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std::vector<MVT::ValueType> RetVals;
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RetVals.push_back(MVT::Other);
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RetVals.push_back(MVT::Flag);
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
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std::vector<MVT::ValueType> NodeTys;
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NodeTys.push_back(MVT::Other); // Returns a chain
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NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
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Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
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InFlag = Chain.getValue(1);
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MVT::ValueType RetTyVT = getValueType(RetTy);
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SDOperand RetVal;
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if (RetTyVT != MVT::isVoid) {
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switch (RetTyVT) {
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default: assert(0 && "Unknown value type to return!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
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Chain = RetVal.getValue(1);
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// Add a note to keep track of whether it is sign or zero extended.
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RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
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MVT::i32, RetVal, DAG.getValueType(RetTyVT));
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RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
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break;
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case MVT::i32:
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RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::f32:
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RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::f64:
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RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::i64:
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SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
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SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
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Lo.getValue(2));
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RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
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Chain = Hi.getValue(1);
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break;
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}
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}
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
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DAG.getConstant(ArgsSize, getPointerTy()));
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MVT::ValueType ActualRetTyVT = RetTyVT;
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if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
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ActualRetTyVT = MVT::i32; // Promote result to i32.
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return std::make_pair(RetVal, Chain);
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}
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SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
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@ -734,6 +937,7 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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}
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case ISD::RET: {
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// FIXME: change this to use flag operands to allow autogen of ret.
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if (N->getNumOperands() == 2) {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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SDOperand Val = Select(N->getOperand(1));
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@ -757,6 +961,26 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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}
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break; // Generated code handles the void case.
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}
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case ISD::CALL:
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// FIXME: This is a workaround for a bug in tblgen.
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{ // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
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// Emits: (CALL:void (tglobaladdr:i32):$dst)
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// Pattern complexity = 2 cost = 1
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SDOperand N1 = N->getOperand(1);
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if (N1.getOpcode() != ISD::TargetGlobalAddress) goto P47Fail;
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SDOperand N2 = N->getOperand(2);
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SDOperand InFlag = SDOperand(0,0);
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SDOperand Chain = N->getOperand(0);
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SDOperand Tmp0 = N1;
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Chain = Select(Chain);
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InFlag = Select(N2);
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SDOperand Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, Chain, InFlag);
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Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
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CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
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return Result.getValue(Op.ResNo);
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}
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P47Fail:;
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}
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return SelectCode(Op);
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@ -57,6 +57,7 @@ def MEMri : Operand<i32> {
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def SDTV8cmpicc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
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@ -83,6 +84,15 @@ def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>;
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def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
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def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
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def SDT_V8Call : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisVT<1, i32>,
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SDTCisVT<2, FlagVT>]>;
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def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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@ -92,8 +102,12 @@ class Pseudo<dag ops, string asmstr, list<dag> pattern>
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: InstV8<ops, asmstr, pattern>;
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def PHI : Pseudo<(ops variable_ops), "PHI", []>;
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def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt",[]>;
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def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKUP $amt", []>;
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def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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def IMPLICIT_DEF : Pseudo<(ops IntRegs:$dst), "!IMPLICIT_DEF $dst", []>;
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def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
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"!FpMOVD", []>; // pseudo 64-bit double move
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@ -523,23 +537,27 @@ def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
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// Section B.24 - Call and Link Instruction, p. 125
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// This is the only Format 1 instruction
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let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
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let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1,
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Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
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// pc-relative call:
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let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
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def CALL : InstV8<(ops IntRegs:$dst), "call $dst", []> {
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def CALL : InstV8<(ops calltarget:$dst),
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"call $dst",
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[(set ICC/*bogus*/, (call tglobaladdr:$dst, ICC/*bogus*/))]> {
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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}
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// indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
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// be an implicit def):
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let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
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// indirect calls
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def JMPLrr : F3_1<2, 0b111000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"jmpl $b+$c, $dst", []>;
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(ops MEMrr:$ptr),
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"jmpl $ptr",
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[(set ICC/*bogus*/, (call ADDRrr:$ptr, ICC/*bogus*/))]>;
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def JMPLri : F3_2<2, 0b111000,
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(ops MEMri:$ptr),
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"jmpl $ptr",
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[(set ICC/*bogus*/, (call ADDRri:$ptr, ICC/*bogus*/))]>;
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}
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// Section B.28 - Read State Register Instructions
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@ -50,6 +50,7 @@ namespace V8ISD {
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namespace {
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class SparcV8TargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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public:
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SparcV8TargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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@ -154,7 +155,6 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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// TODO: FP
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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@ -278,6 +278,9 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// Store remaining ArgRegs to the stack if this is a varargs function.
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if (F.getFunctionType()->isVarArg()) {
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// Remember the vararg offset for the va_start implementation.
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VarArgsFrameOffset = ArgOffset;
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for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg, VReg);
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@ -325,8 +328,208 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
|
||||
bool isVarArg, unsigned CC,
|
||||
bool isTailCall, SDOperand Callee,
|
||||
ArgListTy &Args, SelectionDAG &DAG) {
|
||||
assert(0 && "Unimp");
|
||||
abort();
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
// Count the size of the outgoing arguments.
|
||||
unsigned ArgsSize = 0;
|
||||
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
||||
switch (getValueType(Args[i].second)) {
|
||||
default: assert(0 && "Unknown value type!");
|
||||
case MVT::i1:
|
||||
case MVT::i8:
|
||||
case MVT::i16:
|
||||
case MVT::i32:
|
||||
case MVT::f32:
|
||||
ArgsSize += 4;
|
||||
break;
|
||||
case MVT::i64:
|
||||
case MVT::f64:
|
||||
ArgsSize += 8;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ArgsSize > 4*6)
|
||||
ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
|
||||
else
|
||||
ArgsSize = 0;
|
||||
|
||||
Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
|
||||
DAG.getConstant(ArgsSize, getPointerTy()));
|
||||
|
||||
SDOperand StackPtr, NullSV;
|
||||
std::vector<SDOperand> Stores;
|
||||
std::vector<SDOperand> RegValuesToPass;
|
||||
unsigned ArgOffset = 68;
|
||||
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
||||
SDOperand Val = Args[i].first;
|
||||
MVT::ValueType ObjectVT = Val.getValueType();
|
||||
SDOperand ValToStore;
|
||||
unsigned ObjSize;
|
||||
switch (ObjectVT) {
|
||||
default: assert(0 && "Unhandled argument type!");
|
||||
case MVT::i1:
|
||||
case MVT::i8:
|
||||
case MVT::i16:
|
||||
// Promote the integer to 32-bits. If the input type is signed, use a
|
||||
// sign extend, otherwise use a zero extend.
|
||||
if (Args[i].second->isSigned())
|
||||
Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
|
||||
else
|
||||
Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
|
||||
// FALL THROUGH
|
||||
case MVT::i32:
|
||||
ObjSize = 4;
|
||||
|
||||
if (RegValuesToPass.size() >= 6) {
|
||||
ValToStore = Val;
|
||||
} else {
|
||||
RegValuesToPass.push_back(Val);
|
||||
}
|
||||
break;
|
||||
case MVT::f32:
|
||||
ObjSize = 4;
|
||||
if (RegValuesToPass.size() >= 6) {
|
||||
ValToStore = Val;
|
||||
} else {
|
||||
// Convert this to a FP value in an int reg.
|
||||
int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4);
|
||||
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
|
||||
SDOperand SV = DAG.getSrcValue(0);
|
||||
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
||||
Val, FIPtr, SV);
|
||||
Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV);
|
||||
RegValuesToPass.push_back(Val);
|
||||
}
|
||||
break;
|
||||
case MVT::f64: {
|
||||
ObjSize = 8;
|
||||
// If we can store this directly into the outgoing slot, do so. We can
|
||||
// do this when all ArgRegs are used and if the outgoing slot is aligned.
|
||||
if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
|
||||
ValToStore = Val;
|
||||
break;
|
||||
}
|
||||
|
||||
// Otherwise, convert this to a FP value in int regs.
|
||||
int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
|
||||
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
|
||||
SDOperand SV = DAG.getSrcValue(0);
|
||||
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
||||
Val, FIPtr, SV);
|
||||
Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV);
|
||||
}
|
||||
// FALL THROUGH
|
||||
case MVT::i64:
|
||||
ObjSize = 8;
|
||||
if (RegValuesToPass.size() >= 6) {
|
||||
ValToStore = Val; // Whole thing is passed in memory.
|
||||
break;
|
||||
}
|
||||
|
||||
// Split the value into top and bottom part. Top part goes in a reg.
|
||||
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
|
||||
DAG.getConstant(1, MVT::i32));
|
||||
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
|
||||
DAG.getConstant(0, MVT::i32));
|
||||
RegValuesToPass.push_back(Hi);
|
||||
|
||||
if (RegValuesToPass.size() >= 6) {
|
||||
ValToStore = Lo;
|
||||
} else {
|
||||
RegValuesToPass.push_back(Lo);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (ValToStore.Val) {
|
||||
if (!StackPtr.Val) {
|
||||
StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::SP, MVT::i32);
|
||||
NullSV = DAG.getSrcValue(NULL);
|
||||
}
|
||||
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
||||
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
||||
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
||||
ValToStore, PtrOff, NullSV));
|
||||
}
|
||||
ArgOffset += ObjSize;
|
||||
}
|
||||
|
||||
// Emit all stores, make sure the occur before any copies into physregs.
|
||||
if (!Stores.empty())
|
||||
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
|
||||
|
||||
static const unsigned ArgRegs[] = {
|
||||
V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
|
||||
};
|
||||
|
||||
// Build a sequence of copy-to-reg nodes chained together with token chain
|
||||
// and flag operands which copy the outgoing args into O[0-5].
|
||||
SDOperand InFlag;
|
||||
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
|
||||
Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
|
||||
InFlag = Chain.getValue(1);
|
||||
}
|
||||
|
||||
std::vector<MVT::ValueType> RetVals;
|
||||
RetVals.push_back(MVT::Other);
|
||||
RetVals.push_back(MVT::Flag);
|
||||
|
||||
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
||||
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
||||
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
||||
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
|
||||
|
||||
std::vector<MVT::ValueType> NodeTys;
|
||||
NodeTys.push_back(MVT::Other); // Returns a chain
|
||||
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
||||
Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
|
||||
InFlag = Chain.getValue(1);
|
||||
|
||||
MVT::ValueType RetTyVT = getValueType(RetTy);
|
||||
SDOperand RetVal;
|
||||
if (RetTyVT != MVT::isVoid) {
|
||||
switch (RetTyVT) {
|
||||
default: assert(0 && "Unknown value type to return!");
|
||||
case MVT::i1:
|
||||
case MVT::i8:
|
||||
case MVT::i16:
|
||||
RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
|
||||
Chain = RetVal.getValue(1);
|
||||
|
||||
// Add a note to keep track of whether it is sign or zero extended.
|
||||
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
|
||||
MVT::i32, RetVal, DAG.getValueType(RetTyVT));
|
||||
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
|
||||
break;
|
||||
case MVT::i32:
|
||||
RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
|
||||
Chain = RetVal.getValue(1);
|
||||
break;
|
||||
case MVT::f32:
|
||||
RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
|
||||
Chain = RetVal.getValue(1);
|
||||
break;
|
||||
case MVT::f64:
|
||||
RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
|
||||
Chain = RetVal.getValue(1);
|
||||
break;
|
||||
case MVT::i64:
|
||||
SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
|
||||
SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
|
||||
Lo.getValue(2));
|
||||
RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
|
||||
Chain = Hi.getValue(1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
|
||||
DAG.getConstant(ArgsSize, getPointerTy()));
|
||||
|
||||
MVT::ValueType ActualRetTyVT = RetTyVT;
|
||||
if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
|
||||
ActualRetTyVT = MVT::i32; // Promote result to i32.
|
||||
|
||||
return std::make_pair(RetVal, Chain);
|
||||
}
|
||||
|
||||
SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
|
||||
@ -734,6 +937,7 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
|
||||
}
|
||||
|
||||
case ISD::RET: {
|
||||
// FIXME: change this to use flag operands to allow autogen of ret.
|
||||
if (N->getNumOperands() == 2) {
|
||||
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
|
||||
SDOperand Val = Select(N->getOperand(1));
|
||||
@ -757,6 +961,26 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
|
||||
}
|
||||
break; // Generated code handles the void case.
|
||||
}
|
||||
case ISD::CALL:
|
||||
// FIXME: This is a workaround for a bug in tblgen.
|
||||
{ // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
|
||||
// Emits: (CALL:void (tglobaladdr:i32):$dst)
|
||||
// Pattern complexity = 2 cost = 1
|
||||
SDOperand N1 = N->getOperand(1);
|
||||
if (N1.getOpcode() != ISD::TargetGlobalAddress) goto P47Fail;
|
||||
SDOperand N2 = N->getOperand(2);
|
||||
SDOperand InFlag = SDOperand(0,0);
|
||||
SDOperand Chain = N->getOperand(0);
|
||||
SDOperand Tmp0 = N1;
|
||||
Chain = Select(Chain);
|
||||
InFlag = Select(N2);
|
||||
SDOperand Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, Chain, InFlag);
|
||||
Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
|
||||
CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
|
||||
return Result.getValue(Op.ResNo);
|
||||
}
|
||||
P47Fail:;
|
||||
|
||||
}
|
||||
|
||||
return SelectCode(Op);
|
||||
|
||||
@ -57,6 +57,7 @@ def MEMri : Operand<i32> {
|
||||
|
||||
// Branch targets have OtherVT type.
|
||||
def brtarget : Operand<OtherVT>;
|
||||
def calltarget : Operand<i32>;
|
||||
|
||||
def SDTV8cmpicc :
|
||||
SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
|
||||
@ -83,6 +84,15 @@ def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>;
|
||||
def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
|
||||
def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
|
||||
|
||||
// These are target-independent nodes, but have target-specific formats.
|
||||
def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
|
||||
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
|
||||
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
|
||||
|
||||
def SDT_V8Call : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisVT<1, i32>,
|
||||
SDTCisVT<2, FlagVT>]>;
|
||||
def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -92,8 +102,12 @@ class Pseudo<dag ops, string asmstr, list<dag> pattern>
|
||||
: InstV8<ops, asmstr, pattern>;
|
||||
|
||||
def PHI : Pseudo<(ops variable_ops), "PHI", []>;
|
||||
def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt",[]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKUP $amt", []>;
|
||||
def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
|
||||
"!ADJCALLSTACKDOWN $amt",
|
||||
[(callseq_start imm:$amt)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
|
||||
"!ADJCALLSTACKUP $amt",
|
||||
[(callseq_end imm:$amt)]>;
|
||||
def IMPLICIT_DEF : Pseudo<(ops IntRegs:$dst), "!IMPLICIT_DEF $dst", []>;
|
||||
def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
|
||||
"!FpMOVD", []>; // pseudo 64-bit double move
|
||||
@ -523,23 +537,27 @@ def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
|
||||
|
||||
// Section B.24 - Call and Link Instruction, p. 125
|
||||
// This is the only Format 1 instruction
|
||||
let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
|
||||
let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1,
|
||||
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
|
||||
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
|
||||
// pc-relative call:
|
||||
let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
|
||||
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
|
||||
def CALL : InstV8<(ops IntRegs:$dst), "call $dst", []> {
|
||||
def CALL : InstV8<(ops calltarget:$dst),
|
||||
"call $dst",
|
||||
[(set ICC/*bogus*/, (call tglobaladdr:$dst, ICC/*bogus*/))]> {
|
||||
bits<30> disp;
|
||||
let op = 1;
|
||||
let Inst{29-0} = disp;
|
||||
}
|
||||
|
||||
// indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
|
||||
// be an implicit def):
|
||||
let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
|
||||
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
|
||||
// indirect calls
|
||||
def JMPLrr : F3_1<2, 0b111000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"jmpl $b+$c, $dst", []>;
|
||||
(ops MEMrr:$ptr),
|
||||
"jmpl $ptr",
|
||||
[(set ICC/*bogus*/, (call ADDRrr:$ptr, ICC/*bogus*/))]>;
|
||||
def JMPLri : F3_2<2, 0b111000,
|
||||
(ops MEMri:$ptr),
|
||||
"jmpl $ptr",
|
||||
[(set ICC/*bogus*/, (call ADDRri:$ptr, ICC/*bogus*/))]>;
|
||||
}
|
||||
|
||||
// Section B.28 - Read State Register Instructions
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user