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R600/SI: Use address space in allowsUnalignedMemoryAccesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207126 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -223,10 +223,40 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
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unsigned AddrSpace,
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bool *IsFast) const {
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if (IsFast)
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*IsFast = false;
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// XXX: This depends on the address space and also we may want to revist
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// the alignment values we specify in the DataLayout.
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// TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
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// which isn't a simple VT.
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if (!VT.isSimple() || VT == MVT::Other)
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return false;
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// XXX - CI changes say "Support for unaligned memory accesses" but I don't
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// see what for specifically. The wording everywhere else seems to be the
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// same.
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// 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
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// no alignment restrictions.
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if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
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// Using any pair of GPRs should be the same as any other pair.
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if (IsFast)
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*IsFast = true;
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return VT.bitsGE(MVT::i64);
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}
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// XXX - The only mention I see of this in the ISA manual is for LDS direct
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// reads the "byte address and must be dword aligned". Is it also true for the
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// normal loads and stores?
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if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
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return false;
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// 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
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// byte-address are ignored, thus forcing Dword alignment.
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if (IsFast)
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*IsFast = true;
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return VT.bitsGT(MVT::i32);
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}
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