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make the avx intrinsics 3 address
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105876 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -790,16 +790,20 @@ multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
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!strconcat(OpcodeStr, "_ss")) VR128:$src1,
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VR128:$src2))]>;
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VR128:$src2))]> {
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// int_x86_sse_xxx_ss
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let Constraints = "";
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}
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def V#NAME#SDrr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
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!strconcat(OpcodeStr, "_sd")) VR128:$src1,
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VR128:$src2))]>;
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VR128:$src2))]> {
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// int_x86_sse2_xxx_sd
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let Constraints = "";
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}
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def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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@ -823,16 +827,20 @@ multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
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!strconcat(OpcodeStr, "_ss")) VR128:$src1,
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sse_load_f32:$src2))]>;
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sse_load_f32:$src2))]> {
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// int_x86_sse_xxx_ss
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let Constraints = "";
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}
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def V#NAME#SDrm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, sdmem:$src2),
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!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
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!strconcat(OpcodeStr, "_sd")) VR128:$src1,
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sse_load_f64:$src2))]>;
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sse_load_f64:$src2))]> {
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// int_x86_sse2_xxx_sd
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let Constraints = "";
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}
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def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2),
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