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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 03:29:40 +00:00
Fix integer cast code to handle vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91362 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5196,7 +5196,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
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// SimplifyDemandedBits, which only works if the value has a single use.
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if (SimplifyDemandedBits(Value,
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APInt::getLowBitsSet(
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Value.getValueSizeInBits(),
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Value.getValueType().getScalarType().getSizeInBits(),
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ST->getMemoryVT().getSizeInBits())))
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return SDValue(N, 0);
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}
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@ -2354,6 +2354,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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assert(VT.isFloatingPoint() &&
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Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
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if (Operand.getValueType() == VT) return Operand; // noop conversion.
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assert((!VT.isVector() ||
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VT.getVectorNumElements() ==
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Operand.getValueType().getVectorNumElements()) &&
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"Vector element count mismatch!");
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if (Operand.getOpcode() == ISD::UNDEF)
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return getUNDEF(VT);
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break;
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@ -2361,8 +2365,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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assert(VT.isInteger() && Operand.getValueType().isInteger() &&
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"Invalid SIGN_EXTEND!");
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if (Operand.getValueType() == VT) return Operand; // noop extension
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assert(Operand.getValueType().bitsLT(VT)
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&& "Invalid sext node, dst < src!");
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assert(Operand.getValueType().getScalarType().bitsLT(VT.getScalarType()) &&
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"Invalid sext node, dst < src!");
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assert((!VT.isVector() ||
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VT.getVectorNumElements() ==
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Operand.getValueType().getVectorNumElements()) &&
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"Vector element count mismatch!");
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if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
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return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
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break;
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@ -2370,8 +2378,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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assert(VT.isInteger() && Operand.getValueType().isInteger() &&
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"Invalid ZERO_EXTEND!");
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if (Operand.getValueType() == VT) return Operand; // noop extension
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assert(Operand.getValueType().bitsLT(VT)
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&& "Invalid zext node, dst < src!");
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assert(Operand.getValueType().getScalarType().bitsLT(VT.getScalarType()) &&
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"Invalid zext node, dst < src!");
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assert((!VT.isVector() ||
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VT.getVectorNumElements() ==
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Operand.getValueType().getVectorNumElements()) &&
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"Vector element count mismatch!");
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if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
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return getNode(ISD::ZERO_EXTEND, DL, VT,
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Operand.getNode()->getOperand(0));
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@ -2380,8 +2392,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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assert(VT.isInteger() && Operand.getValueType().isInteger() &&
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"Invalid ANY_EXTEND!");
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if (Operand.getValueType() == VT) return Operand; // noop extension
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assert(Operand.getValueType().bitsLT(VT)
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&& "Invalid anyext node, dst < src!");
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assert(Operand.getValueType().getScalarType().bitsLT(VT.getScalarType()) &&
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"Invalid anyext node, dst < src!");
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assert((!VT.isVector() ||
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VT.getVectorNumElements() ==
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Operand.getValueType().getVectorNumElements()) &&
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"Vector element count mismatch!");
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if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
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// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
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return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
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@ -2390,14 +2406,19 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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assert(VT.isInteger() && Operand.getValueType().isInteger() &&
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"Invalid TRUNCATE!");
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if (Operand.getValueType() == VT) return Operand; // noop truncate
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assert(Operand.getValueType().bitsGT(VT)
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&& "Invalid truncate node, src < dst!");
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assert(Operand.getValueType().getScalarType().bitsGT(VT.getScalarType()) &&
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"Invalid truncate node, src < dst!");
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assert((!VT.isVector() ||
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VT.getVectorNumElements() ==
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Operand.getValueType().getVectorNumElements()) &&
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"Vector element count mismatch!");
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if (OpOpcode == ISD::TRUNCATE)
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return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
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else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
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OpOpcode == ISD::ANY_EXTEND) {
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// If the source is smaller than the dest, we still need an extend.
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if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
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if (Operand.getNode()->getOperand(0).getValueType().getScalarType()
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.bitsLT(VT.getScalarType()))
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return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
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else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT))
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return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
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@ -3743,16 +3764,15 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
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assert(VT == MemVT && "Non-extending load from different memory type!");
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} else {
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// Extending load.
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if (VT.isVector())
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assert(MemVT.getVectorNumElements() == VT.getVectorNumElements() &&
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"Invalid vector extload!");
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else
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assert(MemVT.bitsLT(VT) &&
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"Should only be an extending load, not truncating!");
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assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
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"Cannot sign/zero extend a FP/Vector load!");
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assert(MemVT.getScalarType().bitsLT(VT.getScalarType()) &&
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"Should only be an extending load, not truncating!");
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assert(VT.isInteger() == MemVT.isInteger() &&
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"Cannot convert from FP to Int or Int -> FP!");
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assert(VT.isVector() == MemVT.isVector() &&
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"Cannot use trunc store to convert to or from a vector!");
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assert((!VT.isVector() ||
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VT.getVectorNumElements() == MemVT.getVectorNumElements()) &&
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"Cannot use trunc store to change the number of vector elements!");
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}
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bool Indexed = AM != ISD::UNINDEXED;
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@ -3885,10 +3905,15 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
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if (VT == SVT)
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return getStore(Chain, dl, Val, Ptr, MMO);
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assert(VT.bitsGT(SVT) && "Not a truncation?");
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assert(SVT.getScalarType().bitsLT(VT.getScalarType()) &&
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"Should only be a truncating store, not extending!");
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assert(VT.isInteger() == SVT.isInteger() &&
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"Can't do FP-INT conversion!");
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assert(VT.isVector() == SVT.isVector() &&
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"Cannot use trunc store to convert to or from a vector!");
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assert((!VT.isVector() ||
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VT.getVectorNumElements() == SVT.getVectorNumElements()) &&
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"Cannot use trunc store to change the number of vector elements!");
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SDVTList VTs = getVTList(MVT::Other);
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SDValue Undef = getUNDEF(Ptr.getValueType());
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@ -596,6 +596,17 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
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setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
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for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
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setTruncStoreAction((MVT::SimpleValueType)VT,
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(MVT::SimpleValueType)InnerVT, Expand);
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setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
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setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
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}
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// FIXME: In order to prevent SSE instructions being expanded to MMX ones
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@ -672,8 +683,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
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setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
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setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
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setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
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setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
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setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
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13
test/CodeGen/X86/vec-trunc-store.ll
Normal file
13
test/CodeGen/X86/vec-trunc-store.ll
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@ -0,0 +1,13 @@
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; RUN: llc < %s -march=x86-64 -disable-mmx | grep punpcklwd | count 2
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define void @foo() nounwind {
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%cti69 = trunc <8 x i32> undef to <8 x i16> ; <<8 x i16>> [#uses=1]
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store <8 x i16> %cti69, <8 x i16>* undef
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ret void
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}
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define void @bar() nounwind {
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%cti44 = trunc <4 x i32> undef to <4 x i16> ; <<4 x i16>> [#uses=1]
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store <4 x i16> %cti44, <4 x i16>* undef
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ret void
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}
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