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McARM: Start marking T2 address operands as such, for the benefit of the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -129,6 +129,7 @@ def t2addrmode_imm12 : Operand<i32>,
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let PrintMethod = "printAddrModeImm12Operand";
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let EncoderMethod = "getAddrModeImm12OpValue";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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let ParserMatchClass = MemMode5AsmOperand;
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}
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// ADR instruction labels.
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@ -143,6 +144,7 @@ def t2addrmode_imm8 : Operand<i32>,
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let PrintMethod = "printT2AddrModeImm8Operand";
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let EncoderMethod = "getT2AddrModeImm8OpValue";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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let ParserMatchClass = MemMode5AsmOperand;
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}
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def t2am_imm8_offset : Operand<i32>,
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@ -150,6 +152,7 @@ def t2am_imm8_offset : Operand<i32>,
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[], [SDNPWantRoot]> {
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let PrintMethod = "printT2AddrModeImm8OffsetOperand";
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let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
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let ParserMatchClass = MemMode5AsmOperand;
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}
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// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
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@ -157,6 +160,7 @@ def t2addrmode_imm8s4 : Operand<i32> {
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let PrintMethod = "printT2AddrModeImm8s4Operand";
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let EncoderMethod = "getT2AddrModeImm8s4OpValue";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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let ParserMatchClass = MemMode5AsmOperand;
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}
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def t2am_imm8s4_offset : Operand<i32> {
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@ -169,6 +173,7 @@ def t2addrmode_so_reg : Operand<i32>,
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let PrintMethod = "printT2AddrModeSoRegOperand";
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let EncoderMethod = "getT2AddrModeSORegOpValue";
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let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
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let ParserMatchClass = MemMode5AsmOperand;
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}
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12
test/MC/ARM/thumb2_instructions.s
Normal file
12
test/MC/ARM/thumb2_instructions.s
Normal file
@ -0,0 +1,12 @@
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@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding %s > %t
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@ RUN: FileCheck < %t %s
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.syntax unified
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.text
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@ FIXME: This is not the correct instruction representation, but at least we are
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@ parsing the ldr to something.
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@
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@ CHECK: ldr r0, [r7, #258]
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ldr r0, [r7, #-8]
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