rename isStore -> mayStore to more accurately reflect what it captures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/LinkAllPasses.h

@@ -114,6 +114,7 @@ namespace {
       (void) llvm::createPredicateSimplifierPass();
       (void) llvm::createCodeGenPreparePass();
       (void) llvm::createGVNPass();
+      (void) llvm::createValueInfoPass();
 
       (void)new llvm::IntervalPartition();
       (void)new llvm::FindUsedTypes();

include/llvm/Target/TargetInstrInfo.h

@@ -50,11 +50,11 @@ const unsigned M_BARRIER_FLAG          = 1 << 3;
 const unsigned M_DELAY_SLOT_FLAG       = 1 << 4;
 const unsigned M_LOAD_FLAG             = 1 << 5;
   
-/// M_STORE_FLAG - This flag is set to any instruction that could possibly
+/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
 /// modify memory.  Instructions with this flag set are not necessarily simple
 /// store instructions, they may store a modified value based on their operands,
 /// or may not actually modify anything, for example.
-const unsigned M_STORE_FLAG            = 1 << 6;
+const unsigned M_MAY_STORE_FLAG        = 1 << 6;
   
 const unsigned M_INDIRECT_FLAG         = 1 << 7;
 const unsigned M_IMPLICIT_DEF_FLAG     = 1 << 8;
@@ -283,12 +283,12 @@ public:
     return get(Opcode).Flags & M_LOAD_FLAG;
   }
 
-  /// isStore - Return true if this instruction could possibly modify memory.
+  /// mayStore - Return true if this instruction could possibly modify memory.
   /// Instructions with this flag set are not necessarily simple store
   /// instructions, they may store a modified value based on their operands, or
   /// may not actually modify anything, for example.
-  bool isStore(MachineOpCode Opcode) const {
+  bool mayStore(MachineOpCode Opcode) const {
-    return get(Opcode).Flags & M_STORE_FLAG;
+    return get(Opcode).Flags & M_MAY_STORE_FLAG;
   }
   
   /// hasDelaySlot - Returns true if the specified instruction has a delay slot

include/llvm/Transforms/Scalar.h

@@ -337,6 +337,12 @@ FunctionPass *createGVNPREPass();
 //
 FunctionPass *createGVNPass();
 
+//===----------------------------------------------------------------------===//
+//
+// ValueInfo - This pass performs  FIXME
+//
+FunctionPass *createValueInfoPass();
+
 //===----------------------------------------------------------------------===//
 //
 // CodeGenPrepare - This pass prepares a function for instruction selection.

lib/CodeGen/BranchFolding.cpp

@@ -353,7 +353,7 @@ static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
     const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
     if (TID.Flags & M_CALL_FLAG)
       Time += 10;
-    else if (TID.Flags & (M_LOAD_FLAG|M_STORE_FLAG))
+    else if (TID.Flags & (M_LOAD_FLAG|M_MAY_STORE_FLAG))
       Time += 2;
     else
       ++Time;

lib/Target/ARM/ARMInstrInfo.td

@@ -892,7 +892,7 @@ def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
                [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
 
 // Store doubleword
-let isStore = 1 in
+let mayStore = 1 in
 def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
                "str", "d $src, $addr",
                []>, Requires<[IsARM, HasV5T]>;
@@ -945,7 +945,7 @@ def LDM : AXI4<0x0, (outs),
                LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
                []>;
 
-let isStore = 1 in
+let mayStore = 1 in
 def STM : AXI4<0x0, (outs),
                (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
                StFrm, "stm${p}${addr:submode} $addr, $src1",

lib/Target/ARM/ARMInstrThumb.td

@@ -294,7 +294,7 @@ def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
                    "str $src, $addr",
                    [(store GPR:$src, t_addrmode_sp:$addr)]>;
 
-let isStore = 1 in {
+let mayStore = 1 in {
 // Special instruction for spill. It cannot clobber condition register
 // when it's expanded by eliminateCallFramePseudoInstr().
 def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
@@ -311,7 +311,7 @@ let isLoad = 1 in
 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
                "pop $dst1", []>;
 
-let isStore = 1 in
+let mayStore = 1 in
 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
                 "push $src1", []>;
 

lib/Target/ARM/ARMInstrVFP.td

@@ -122,7 +122,7 @@ def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
                   []>;
 } // isLoad
 
-let isStore = 1 in {
+let mayStore = 1 in {
 def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
                            variable_ops),
                  "fstm${addr:submode}d${p} ${addr:base}, $src1",
@@ -132,7 +132,7 @@ def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
                            variable_ops),
                  "fstm${addr:submode}s${p} ${addr:base}, $src1",
                  []>;
-} // isStore
+} // mayStore
 
 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
 

lib/Target/ARM/ARMRegisterInfo.cpp

@@ -905,7 +905,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
         MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
       else  // tLDR has an extra register operand.
         MI.addOperand(MachineOperand::CreateReg(0, false));
-    } else if (TII.isStore(Opcode)) {
+    } else if (TII.mayStore(Opcode)) {
       // FIXME! This is horrific!!! We need register scavenging.
       // Our temporary workaround has marked r3 unavailable. Of course, r3 is
       // also a ABI register so it's possible that is is the register that is

lib/Target/IA64/IA64InstrInfo.td

@@ -541,7 +541,7 @@ def CADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR
 def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2),
   "sub $dst = $imm, $src2">, isA;
 
-let isStore = 1 in {
+let mayStore = 1 in {
   def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
     "st1 [$dstPtr] = $value">, isM;
   def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),

lib/Target/PowerPC/PPCHazardRecognizers.cpp

@@ -73,7 +73,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
   const TargetInstrDescriptor &TID = TII.get(Opcode);
   
   isLoad  = TID.Flags & M_LOAD_FLAG;
-  isStore = TID.Flags & M_STORE_FLAG;
+  isStore = TID.Flags & M_MAY_STORE_FLAG;
   
   unsigned TSFlags = TID.TSFlags;
   

lib/Target/PowerPC/PPCInstr64Bit.td

@@ -513,7 +513,7 @@ def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
                     RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
                     isPPC64;
 
-let isStore = 1 in
+let mayStore = 1 in
 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
                    "stdux $rS, $dst", LdStSTD,
                    []>, isPPC64;

lib/Target/PowerPC/PPCInstrInfo.td

@@ -638,7 +638,7 @@ def STWX  : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
                    [(store GPRC:$rS, xaddr:$dst)]>,
                    PPC970_DGroup_Cracked;
                    
-let isStore = 1 in {
+let mayStore = 1 in {
 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
                    "stwux $rS, $rA, $rB", LdStGeneral,
                    []>;

lib/Target/Target.td

@@ -191,7 +191,7 @@ class Instruction {
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
   bit isLoad       = 0;     // Is this instruction a load instruction?
-  bit isStore      = 0;     // Is this instruction a store instruction?
+  bit mayStore     = 0;     // Can this instruction modify memory?
   bit isImplicitDef = 0;    // Is this instruction an implicit def instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?

lib/Target/TargetSelectionDAG.td

@@ -189,7 +189,7 @@ def SDNPHasChain    : SDNodeProperty;   // R/W chain operand and result
 def SDNPOutFlag     : SDNodeProperty;   // Write a flag result
 def SDNPInFlag      : SDNodeProperty;   // Read a flag operand
 def SDNPOptInFlag   : SDNodeProperty;   // Optionally read a flag operand
-def SDNPMayStore    : SDNodeProperty;   // May write to memory, sets 'isStore'.
+def SDNPMayStore    : SDNodeProperty;   // May write to memory, sets 'mayStore'.
 
 //===----------------------------------------------------------------------===//
 // Selection DAG Node definitions.

utils/TableGen/CodeGenInstruction.cpp

@@ -85,7 +85,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   isLoad       = R->getValueAsBit("isLoad");
-  isStore      = R->getValueAsBit("isStore");
+  mayStore     = R->getValueAsBit("mayStore");
   isImplicitDef= R->getValueAsBit("isImplicitDef");
   bool isTwoAddress = R->getValueAsBit("isTwoAddress");
   isPredicable = R->getValueAsBit("isPredicable");

utils/TableGen/CodeGenInstruction.h

@@ -95,7 +95,7 @@ namespace llvm {
     bool isBarrier;
     bool isCall;
     bool isLoad;
-    bool isStore;
+    bool mayStore;
     bool isImplicitDef;
     bool isPredicable;
     bool isConvertibleToThreeAddress;

utils/TableGen/InstrInfoEmitter.cpp

@@ -143,13 +143,13 @@ void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
 
 class InstAnalyzer {
   const CodeGenDAGPatterns &CDP;
-  bool &isStore;
+  bool &mayStore;
   bool &isLoad;
   bool &NeverHasSideEffects;
 public:
   InstAnalyzer(const CodeGenDAGPatterns &cdp,
-               bool &isstore, bool &isload, bool &nhse)
+               bool &maystore, bool &isload, bool &nhse)
-    : CDP(cdp), isStore(isstore), isLoad(isload), NeverHasSideEffects(nhse) {
+    : CDP(cdp), mayStore(maystore), isLoad(isload), NeverHasSideEffects(nhse) {
   }
   
   void Analyze(Record *InstRecord) {
@@ -176,11 +176,11 @@ private:
       
       // If node writes to memory, it obviously stores to memory.
       if (OpInfo.hasProperty(SDNPMayStore)) {
-        isStore = true;
+        mayStore = true;
       } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
         // If this is an intrinsic, analyze it.
         if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
-          isStore = true;  // Intrinsics that can write to memory are 'isStore'.
+          mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
       }
     }
 
@@ -191,21 +191,22 @@ private:
 };
 
 void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, 
-                                        bool &isStore, bool &isLoad, 
+                                        bool &mayStore, bool &isLoad, 
                                         bool &NeverHasSideEffects) {
-  isStore = isLoad = NeverHasSideEffects = false;
+  mayStore = isLoad = NeverHasSideEffects = false;
   
-  InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
+  InstAnalyzer(CDP, mayStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
 
-  // InstAnalyzer only correctly analyzes isStore so far.
+  // InstAnalyzer only correctly analyzes mayStore so far.
-  if (Inst.isStore) {  // If the .td file explicitly sets isStore, use it.
+  if (Inst.mayStore) {  // If the .td file explicitly sets mayStore, use it.
     // If we decided that this is a store from the pattern, then the .td file
     // entry is redundant.
-    if (isStore)
+    if (mayStore)
-      fprintf(stderr, "Warning: isStore flag explicitly set on instruction '%s'"
+      fprintf(stderr, 
+              "Warning: mayStore flag explicitly set on instruction '%s'"
               " but flag already inferred from pattern.\n", 
               Inst.getName().c_str());
-    isStore = true;
+    mayStore = true;
   }
 
   // These two override everything.
@@ -280,8 +281,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   const OperandInfoMapTy &OpInfo,
                                   std::ostream &OS) {
   // Determine properties of the instruction from its pattern.
-  bool isStore, isLoad, NeverHasSideEffects;
+  bool mayStore, isLoad, NeverHasSideEffects;
-  InferFromPattern(Inst, isStore, isLoad, NeverHasSideEffects);
+  InferFromPattern(Inst, mayStore, isLoad, NeverHasSideEffects);
   
   if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
     std::cerr << "error: Instruction '" << Inst.getName()
@@ -308,7 +309,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
   if (Inst.isCall)       OS << "|M_CALL_FLAG";
   if (isLoad)            OS << "|M_LOAD_FLAG";
-  if (isStore)           OS << "|M_STORE_FLAG";
+  if (mayStore)          OS << "|M_MAY_STORE_FLAG";
   if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
   if (Inst.isPredicable) OS << "|M_PREDICABLE";
   if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";