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Reapply 154397. Original message:
Fix a dagcombine optimization which assumes that the vsetcc result type is always of the same size as the compared values. This is ture for SSE/AVX/NEON but not for all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154490 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4354,12 +4354,17 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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// Only do this before legalize for now.
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if (VT.isVector() && !LegalOperations) {
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EVT N0VT = N0.getOperand(0).getValueType();
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// We know that the # elements of the results is the same as the
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// # elements of the compare (and the # elements of the compare result
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// for that matter). Check to see that they are the same size. If so,
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// we know that the element size of the sext'd result matches the
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// element size of the compare operands.
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if (VT.getSizeInBits() == N0VT.getSizeInBits())
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// On some architectures (such as SSE/NEON/etc) the SETCC result type is
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// of the same size as the compared operands. Only optimize sext(setcc())
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// if this is the case.
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EVT SVT = TLI.getSetCCResultType(N0VT);
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// We know that the # elements of the results is the same as the
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// # elements of the compare (and the # elements of the compare result
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// for that matter). Check to see that they are the same size. If so,
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// we know that the element size of the sext'd result matches the
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// element size of the compare operands.
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if (VT.getSizeInBits() == SVT.getSizeInBits())
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return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
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N0.getOperand(1),
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cast<CondCodeSDNode>(N0.getOperand(2))->get());
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@ -4373,11 +4378,13 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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EVT MatchingVectorType =
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EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
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N0VT.getVectorNumElements());
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SDValue VsetCC =
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DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
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N0.getOperand(1),
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cast<CondCodeSDNode>(N0.getOperand(2))->get());
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return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
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if (SVT == MatchingVectorType) {
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SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
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N0.getOperand(0), N0.getOperand(1),
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cast<CondCodeSDNode>(N0.getOperand(2))->get());
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return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
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}
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}
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}
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