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[X86] Silvermont new scheduler model
This model is not final and work is still in progress. However there are substantial improvements on integer tests mainly because of better RAL with new scheduler. Differential Revision: http://reviews.llvm.org/D3451 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206957 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alexey Volkov
parent
bf255f5d5a
commit
2e5f39ee0f
@ -1,4 +1,4 @@
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//===- X86ScheduleSLM.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
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//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -7,662 +7,222 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the Intel Atom
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// (Silvermont) processor.
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// This file defines the machine model for Intal Silvermont to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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def IEC_RSV0 : FuncUnit;
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def IEC_RSV1 : FuncUnit;
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def FPC_RSV0 : FuncUnit;
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def FPC_RSV1 : FuncUnit;
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def MEC_RSV : FuncUnit;
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def SLMItineraries : ProcessorItineraries<
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[ IEC_RSV0, IEC_RSV1, FPC_RSV0, FPC_RSV1, MEC_RSV ],
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[], [
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// [InstrStage<N, [FPC_RSV0, FPC_RSV1]>]
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// [InstrStage<N, [FPC_RSV0, FPC_RSV1], 0>, InstrStage<N, [MEC_RSV]>]
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// [InstrStage<N, [IEC_RSV0, IEC_RSV1]>]
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// [InstrStage<N, [IEC_RSV0, IEC_RSV1], 0>,InstrStage<N,[MEC_RSV]>]
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//
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// Default is 1 cycle, IEC_RSV0 or IEC_RSV1
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//InstrItinData<IIC_DEFAULT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_ALU_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_LEA, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_LEA_16, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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// mul
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InstrItinData<IIC_MUL8, [InstrStage<4, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_MUL16_MEM, [InstrStage<4, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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InstrItinData<IIC_MUL16_REG, [InstrStage<4, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_MUL32_MEM, [InstrStage<3, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<3, [MEC_RSV]>] >,
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InstrItinData<IIC_MUL32_REG, [InstrStage<3, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_MUL64, [InstrStage<4, [IEC_RSV0, IEC_RSV1]>] >,
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// imul by al, ax, eax, rax
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InstrItinData<IIC_IMUL8, [InstrStage<6, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IMUL16_MEM, [InstrStage<6, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<6, [MEC_RSV]>] >,
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InstrItinData<IIC_IMUL16_REG, [InstrStage<6, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IMUL32_MEM, [InstrStage<6, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<6, [MEC_RSV]>] >,
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InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IMUL64, [InstrStage<6, [IEC_RSV0, IEC_RSV1]>] >,
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// imul reg by reg|mem
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InstrItinData<IIC_IMUL16_RM, [InstrStage<4, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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InstrItinData<IIC_IMUL16_RR, [InstrStage<4, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IMUL32_RM, [InstrStage<3, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<3, [MEC_RSV]>] >,
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InstrItinData<IIC_IMUL32_RR, [InstrStage<3, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IMUL64_RM, [InstrStage<4, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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InstrItinData<IIC_IMUL64_RR, [InstrStage<4, [IEC_RSV0, IEC_RSV1]>] >,
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// imul reg = reg/mem * imm
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InstrItinData<IIC_IMUL16_RRI, [InstrStage<4, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IMUL32_RRI, [InstrStage<3, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IMUL64_RRI, [InstrStage<4, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IMUL16_RMI, [InstrStage<4, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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InstrItinData<IIC_IMUL32_RMI, [InstrStage<3, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<3, [MEC_RSV]>] >,
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InstrItinData<IIC_IMUL64_RMI, [InstrStage<4, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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// idiv - min latency
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InstrItinData<IIC_IDIV8, [InstrStage<34, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IDIV16, [InstrStage<35, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IDIV32, [InstrStage<35, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_IDIV64, [InstrStage<49, [IEC_RSV0, IEC_RSV1]>] >,
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// div - min latency
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InstrItinData<IIC_DIV8_REG, [InstrStage<25, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_DIV8_MEM, [InstrStage<25, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<25, [MEC_RSV]>] >,
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InstrItinData<IIC_DIV16, [InstrStage<26, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_DIV32, [InstrStage<26, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_DIV64, [InstrStage<38, [IEC_RSV0, IEC_RSV1]>] >,
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// neg/not/inc/dec
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InstrItinData<IIC_UNARY_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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// add/sub/and/or/xor/adc/sbc/cmp/test
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InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_BIN_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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// adc/sbb
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InstrItinData<IIC_BIN_CARRY_NONMEM, [InstrStage<2, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_BIN_CARRY_MEM, [InstrStage<2, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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// shift/rotate
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InstrItinData<IIC_SR, [InstrStage<1, [IEC_RSV0], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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// shift double
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InstrItinData<IIC_SHD16_REG_IM, [InstrStage<2, [IEC_RSV0]>] >,
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InstrItinData<IIC_SHD16_REG_CL, [InstrStage<4, [IEC_RSV0]>] >,
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InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<2, [IEC_RSV0], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<4, [IEC_RSV0], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [IEC_RSV0]>] >,
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InstrItinData<IIC_SHD32_REG_CL, [InstrStage<4, [IEC_RSV0]>] >,
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InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<2, [IEC_RSV0], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [IEC_RSV0], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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InstrItinData<IIC_SHD64_REG_IM, [InstrStage<2, [IEC_RSV0]>] >,
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InstrItinData<IIC_SHD64_REG_CL, [InstrStage<4, [IEC_RSV0]>] >,
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InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<2, [IEC_RSV0], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<4, [IEC_RSV0], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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// cmov
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InstrItinData<IIC_CMOV16_RM, [InstrStage<2, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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InstrItinData<IIC_CMOV16_RR, [InstrStage<2, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_CMOV32_RM, [InstrStage<2, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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InstrItinData<IIC_CMOV32_RR, [InstrStage<2, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_CMOV64_RM, [InstrStage<2, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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InstrItinData<IIC_CMOV64_RR, [InstrStage<2, [IEC_RSV0, IEC_RSV1]>] >,
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// set
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InstrItinData<IIC_SET_M, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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InstrItinData<IIC_SET_R, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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// jcc
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InstrItinData<IIC_Jcc, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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// jcxz/jecxz/jrcxz
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InstrItinData<IIC_JCXZ, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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// jmp rel
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InstrItinData<IIC_JMP_REL, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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// jmp indirect
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InstrItinData<IIC_JMP_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_JMP_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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// jmp far
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InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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// loop/loope/loopne
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InstrItinData<IIC_LOOP, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_LOOPE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_LOOPNE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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// call - all but reg/imm
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InstrItinData<IIC_CALL_RI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_CALL_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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//ret
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InstrItinData<IIC_RET, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_RET_IMM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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//sign extension movs
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InstrItinData<IIC_MOVSX, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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//zero extension movs
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InstrItinData<IIC_MOVZX, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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InstrItinData<IIC_REP_MOVS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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InstrItinData<IIC_REP_STOS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
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// SSE binary operations
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// arithmetic fp scalar
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InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<3, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_ALU_F32S_RM, [InstrStage<3, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<3, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<3, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_ALU_F64S_RM, [InstrStage<3, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<3, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_MUL_F32S_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_MUL_F32S_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<1, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_MUL_F64S_RR, [InstrStage<2, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_MUL_F64S_RM, [InstrStage<2, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<13, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<13, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<13, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<13, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<13, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<13, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<6, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<6, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<6, [MEC_RSV]>] >,
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// arithmetic fp parallel
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InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<3, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_ALU_F32P_RM, [InstrStage<3, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<3, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_MUL_F32P_RR, [InstrStage<2, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_MUL_F32P_RM, [InstrStage<2, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<2, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<4, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<27, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<27, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<27, [MEC_RSV]>] >,
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InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<27, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<27, [FPC_RSV0, FPC_RSV1], 0>,
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InstrStage<27, [MEC_RSV]>] >,
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// bitwise parallel
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InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
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InstrItinData<IIC_SSE_BIT_P_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
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||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
|
||||
// arithmetic int parallel
|
||||
InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_INTALU_P_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
|
||||
// multiply int parallel
|
||||
InstrItinData<IIC_SSE_INTMUL_P_RR, [InstrStage<5, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_INTMUL_P_RM, [InstrStage<5, [FPC_RSV0], 0>,
|
||||
InstrStage<5, [MEC_RSV]>] >,
|
||||
|
||||
// shift parallel
|
||||
InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<2, [FPC_RSV0], 0>,
|
||||
InstrStage<2, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [FPC_RSV0]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_INTSHDQ_P_RI, [InstrStage<1, [FPC_RSV0]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_SHUFP, [InstrStage<1, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_PSHUF_RI, [InstrStage<1, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_PSHUF_MI, [InstrStage<1, [FPC_RSV0], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [FPC_RSV0]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_SQRTPS_RR, [InstrStage<26, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_SQRTPS_RM, [InstrStage<26, [FPC_RSV0], 0>,
|
||||
InstrStage<26, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_SQRTSS_RR, [InstrStage<13, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_SQRTSS_RM, [InstrStage<13, [FPC_RSV0], 0>,
|
||||
InstrStage<13, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_SQRTPD_RR, [InstrStage<26, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_SQRTPD_RM, [InstrStage<26, [FPC_RSV0], 0>,
|
||||
InstrStage<26, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_SQRTSD_RR, [InstrStage<13, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_SQRTSD_RM, [InstrStage<13, [FPC_RSV0], 0>,
|
||||
InstrStage<13, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<9, [FPC_RSV0], 0>,
|
||||
InstrStage<9, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_SSE_RCPS_RM, [InstrStage<4, [FPC_RSV0], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_MOVMSK, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MASKMOV, [InstrStage<5, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PINSRW, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PABS_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MOV_S_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_MOV_S_MR, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MOVA_P_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_MOVA_P_MR, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_MOV_LH, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_LDDQU, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_MOVDQ, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MOVD_ToGP, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_MOVNT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_PREFETCH, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PAUSE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MFENCE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_SFENCE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_STMXCSR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<6, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<6, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<6, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<9, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<9, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<9, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<9, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<9, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<9, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<9, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<5, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<5, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PSIGN_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_SSE_PMADD, [InstrStage<5, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PMULHRSW, [InstrStage<5, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PALIGNRR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PALIGNRM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_MWAIT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MONITOR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
// conversions
|
||||
// to/from PD ...
|
||||
InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<5, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<5, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<5, [MEC_RSV]>] >,
|
||||
// to/from PS except to/from PD and PS2PI
|
||||
InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
|
||||
// MMX MOVs
|
||||
InstrItinData<IIC_MMX_MOV_MM_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_MOV_REG_MM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_MOVQ_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_MOVQ_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// other MMX
|
||||
InstrItinData<IIC_MMX_ALU_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_ALU_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_ALUQ_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_ALUQ_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PHADDSUBW_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PHADDSUBW_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PHADDSUBD_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PHADDSUBD_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PMUL, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_MISC_FUNC_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_MISC_FUNC_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PSADBW, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_SHIFT_RI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_SHIFT_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_SHIFT_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_UNPCK_H_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_UNPCK_H_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_UNPCK_L, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PCK_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PCK_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PSHUF, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PEXTR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_PINSRW, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_MASKMOV, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// conversions
|
||||
// from/to PD
|
||||
InstrItinData<IIC_MMX_CVT_PD_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_CVT_PD_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// from/to PI
|
||||
InstrItinData<IIC_MMX_CVT_PS_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MMX_CVT_PS_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_CMPX_LOCK, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_FILD, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FLD, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FLD80, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_FST, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FST80, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FIST, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_FLDZ, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FUCOM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FUCOMI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FCOMI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FNSTSW, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FNSTCW, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FLDCW, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FNINIT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FFREE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FNCLEX, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_WAIT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FXAM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FNOP, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FLDL, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_F2XM1, [InstrStage<88, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_FYL2X, [InstrStage<296, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_FPTAN, [InstrStage<281, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_FPATAN, [InstrStage<296, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_FXTRACT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FPREM1, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FPSTP, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FPREM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FYL2XP1, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FSINCOS, [InstrStage<281, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_FRNDINT, [InstrStage<25, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_FSCALE, [InstrStage<74, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_FCOMPP, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FXSAVE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FXRSTOR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_FXCH, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
|
||||
// System instructions
|
||||
InstrItinData<IIC_CPUID, [InstrStage<60, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_INT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_INT3, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_INVD, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_INVLPG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_IRET, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_HLT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LXS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LTR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_RDTSC, [InstrStage<30, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_RSM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SIDT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SGDT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SLDT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_STR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SWAPGS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SYSCALL, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SYS_ENTER_EXIT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_IN_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_IN_RI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_OUT_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_OUT_IR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_INS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_MOV_REG_DR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MOV_DR_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// worst case for mov REG_CRx
|
||||
InstrItinData<IIC_MOV_REG_CR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MOV_CR_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_MOV_REG_SR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MOV_MEM_SR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MOV_SR_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MOV_SR_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// LAR
|
||||
InstrItinData<IIC_LAR_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LAR_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// LSL
|
||||
InstrItinData<IIC_LSL_RM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LSL_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_LGDT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LIDT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LLDT_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LLDT_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// push control register, segment registers
|
||||
InstrItinData<IIC_PUSH_CS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_PUSH_SR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// pop control register, segment registers
|
||||
InstrItinData<IIC_POP_SR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_POP_SR_SS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// VERR, VERW
|
||||
InstrItinData<IIC_VERR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_VERW_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_VERW_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// WRMSR, RDMSR
|
||||
InstrItinData<IIC_WRMSR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_RDMSR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_RDPMC, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
// SMSW, LMSW
|
||||
InstrItinData<IIC_SMSW, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LMSW_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LMSW_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_ENTER, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LEAVE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_POP_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_POP_REG16, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_POP_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_POP_F, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_POP_FD, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_POP_A, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_PUSH_IMM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_PUSH_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_PUSH_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_PUSH_F, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_PUSH_A, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
|
||||
InstrItinData<IIC_BSWAP, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_BIT_SCAN_MEM, [InstrStage<10, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<10, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_BIT_SCAN_REG, [InstrStage<10, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MOVS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_STOS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SCAS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CMPS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MOV, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_MOV_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_AHF, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_BT_MI, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_BT_MR, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_BT_RI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_BT_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_BTX_MI, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_BTX_MR, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_BTX_RI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_BTX_RR, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_XCHG_REG, [InstrStage<5, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_XCHG_MEM, [InstrStage<5, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<5, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_XADD_REG, [InstrStage<5, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_XADD_MEM, [InstrStage<5, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<5, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_CMPXCHG_MEM, [InstrStage<6, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CMPXCHG_REG, [InstrStage<6, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CMPXCHG_MEM8, [InstrStage<6, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<6, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_CMPXCHG_REG8, [InstrStage<6, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<6, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_CMPXCHG_8B, [InstrStage<6, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CMPXCHG_16B, [InstrStage<6, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_LODS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_OUTS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CLC, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CLD, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CLI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CMC, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CLTS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_STC, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_STI, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_STD, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_XLAT, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_AAA, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_AAD, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_AAM, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_AAS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_DAA, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_DAS, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_BOUND, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_ARPL_REG, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_ARPL_MEM, [InstrStage<1, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_MOVBE, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_AES, [InstrStage<8, [FPC_RSV0]>] >,
|
||||
InstrItinData<IIC_BLEND_NOMEM, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_BLEND_MEM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_BIT_SCAN_MEM, [InstrStage<10, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<10, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_BIT_SCAN_REG, [InstrStage<10, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CBW, [InstrStage<4, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CRC32_REG, [InstrStage<3, [IEC_RSV0, IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_CRC32_MEM, [InstrStage<3, [IEC_RSV0, IEC_RSV1], 0>,
|
||||
InstrStage<3, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_DPPD_RR, [InstrStage<12, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_DPPD_RM, [InstrStage<12, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<12, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_DPPS_RR, [InstrStage<15, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_DPPS_RM, [InstrStage<15, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<15, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_MMX_EMMS, [InstrStage<10, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_EXTRACTPS_RR, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_EXTRACTPS_RM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_INSERTPS_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_INSERTPS_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_MPSADBW_RR, [InstrStage<1, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_MPSADBW_RM, [InstrStage<1, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<1, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_PMULLD_RR, [InstrStage<11, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PMULLD_RM, [InstrStage<11, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<11, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_ROUNDPS_REG, [InstrStage<5, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_ROUNDPS_MEM, [InstrStage<5, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<5, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_ROUNDPD_REG, [InstrStage<4, [FPC_RSV0, FPC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_ROUNDPD_MEM, [InstrStage<4, [FPC_RSV0, FPC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_POPCNT_RR, [InstrStage<4, [IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_POPCNT_RM, [InstrStage<4, [IEC_RSV1], 0>,
|
||||
InstrStage<4, [MEC_RSV]>] >,
|
||||
InstrItinData<IIC_SSE_PCLMULQDQ_RR, [InstrStage<10, [IEC_RSV1]>] >,
|
||||
InstrItinData<IIC_SSE_PCLMULQDQ_RM, [InstrStage<10, [IEC_RSV1], 0>,
|
||||
InstrStage<10, [MEC_RSV]>] >,
|
||||
|
||||
InstrItinData<IIC_NOP, [InstrStage<1, [IEC_RSV0, IEC_RSV1]>] >
|
||||
]>;
|
||||
|
||||
// Silvermont machine model.
|
||||
def SLMModel : SchedMachineModel {
|
||||
let IssueWidth = 2; // Allows 2 instructions per scheduling group.
|
||||
let MinLatency = 1; // InstrStage cycles overrides MinLatency.
|
||||
// OperandCycles may be used for expected latency.
|
||||
let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
|
||||
let HighLatency = 30;// Expected, may be overriden by OperandCycles.
|
||||
// All x86 instructions are modeled as a single micro-op, and SLM can decode 2
|
||||
// instructions per cycle.
|
||||
let IssueWidth = 2;
|
||||
let MicroOpBufferSize = 32; // Based on the reorder buffer.
|
||||
let LoadLatency = 3;
|
||||
let MispredictPenalty = 10;
|
||||
|
||||
let Itineraries = SLMItineraries;
|
||||
// FIXME: SSE4 is unimplemented. This flag is set to allow
|
||||
// the scheduler to assign a default model to unrecognized opcodes.
|
||||
let CompleteModel = 0;
|
||||
}
|
||||
|
||||
let SchedModel = SLMModel in {
|
||||
|
||||
// Silveromnt has 5 reservation stations for micro-ops
|
||||
|
||||
def IEC_RSV0 : ProcResource<1>;
|
||||
def IEC_RSV1 : ProcResource<1>;
|
||||
def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
|
||||
def FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
|
||||
def MEC_RSV : ProcResource<1>;
|
||||
|
||||
// Many micro-ops are capable of issuing on multiple ports.
|
||||
def IEC_RSV01 : ProcResGroup<[IEC_RSV0, IEC_RSV1]>;
|
||||
def FPC_RSV01 : ProcResGroup<[FPC_RSV0, FPC_RSV1]>;
|
||||
|
||||
def SMDivider : ProcResource<1>;
|
||||
def SMFPMultiplier : ProcResource<1>;
|
||||
def SMFPDivider : ProcResource<1>;
|
||||
|
||||
// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
|
||||
// cycles after the memory operand.
|
||||
def : ReadAdvance<ReadAfterLd, 3>;
|
||||
|
||||
// Many SchedWrites are defined in pairs with and without a folded load.
|
||||
// Instructions with folded loads are usually micro-fused, so they only appear
|
||||
// as two micro-ops when queued in the reservation station.
|
||||
// This multiclass defines the resource usage for variants with and without
|
||||
// folded loads.
|
||||
multiclass SMWriteResPair<X86FoldableSchedWrite SchedRW,
|
||||
ProcResourceKind ExePort,
|
||||
int Lat> {
|
||||
// Register variant is using a single cycle on ExePort.
|
||||
def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
|
||||
|
||||
// Memory variant also uses a cycle on MEC_RSV and adds 3 cycles to the
|
||||
// latency.
|
||||
def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> {
|
||||
let Latency = !add(Lat, 3);
|
||||
}
|
||||
}
|
||||
|
||||
// A folded store needs a cycle on MEC_RSV for the store data, but it does not
|
||||
// need an extra port cycle to recompute the address.
|
||||
def : WriteRes<WriteRMW, [MEC_RSV]>;
|
||||
|
||||
def : WriteRes<WriteStore, [IEC_RSV01, MEC_RSV]>;
|
||||
def : WriteRes<WriteLoad, [MEC_RSV]> { let Latency = 3; }
|
||||
def : WriteRes<WriteMove, [IEC_RSV01]>;
|
||||
def : WriteRes<WriteZero, []>;
|
||||
|
||||
defm : SMWriteResPair<WriteALU, IEC_RSV01, 1>;
|
||||
defm : SMWriteResPair<WriteIMul, IEC_RSV1, 3>;
|
||||
defm : SMWriteResPair<WriteShift, IEC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteJump, IEC_RSV1, 1>;
|
||||
|
||||
// This is for simple LEAs with one or two input operands.
|
||||
// The complex ones can only execute on port 1, and they require two cycles on
|
||||
// the port to read all inputs. We don't model that.
|
||||
def : WriteRes<WriteLEA, [IEC_RSV1]>;
|
||||
|
||||
// This is quite rough, latency depends on the dividend.
|
||||
def : WriteRes<WriteIDiv, [IEC_RSV01, SMDivider]> {
|
||||
let Latency = 25;
|
||||
let ResourceCycles = [1, 25];
|
||||
}
|
||||
def : WriteRes<WriteIDivLd, [MEC_RSV, IEC_RSV01, SMDivider]> {
|
||||
let Latency = 29;
|
||||
let ResourceCycles = [1, 1, 25];
|
||||
}
|
||||
|
||||
// Scalar and vector floating point.
|
||||
defm : SMWriteResPair<WriteFAdd, FPC_RSV1, 3>;
|
||||
defm : SMWriteResPair<WriteFRcp, FPC_RSV0, 5>;
|
||||
defm : SMWriteResPair<WriteFSqrt, FPC_RSV0, 15>;
|
||||
defm : SMWriteResPair<WriteCvtF2I, FPC_RSV01, 4>;
|
||||
defm : SMWriteResPair<WriteCvtI2F, FPC_RSV01, 4>;
|
||||
defm : SMWriteResPair<WriteCvtF2F, FPC_RSV01, 4>;
|
||||
defm : SMWriteResPair<WriteFShuffle, FPC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteFBlend, FPC_RSV0, 1>;
|
||||
|
||||
// This is quite rough, latency depends on precision
|
||||
def : WriteRes<WriteFMul, [FPC_RSV0, SMFPMultiplier]> {
|
||||
let Latency = 5;
|
||||
let ResourceCycles = [1, 2];
|
||||
}
|
||||
def : WriteRes<WriteFMulLd, [MEC_RSV, FPC_RSV0, SMFPMultiplier]> {
|
||||
let Latency = 8;
|
||||
let ResourceCycles = [1, 1, 2];
|
||||
}
|
||||
|
||||
def : WriteRes<WriteFDiv, [FPC_RSV0, SMFPDivider]> {
|
||||
let Latency = 34;
|
||||
let ResourceCycles = [1, 34];
|
||||
}
|
||||
def : WriteRes<WriteFDivLd, [MEC_RSV, FPC_RSV0, SMFPDivider]> {
|
||||
let Latency = 37;
|
||||
let ResourceCycles = [1, 1, 34];
|
||||
}
|
||||
|
||||
// Vector integer operations.
|
||||
defm : SMWriteResPair<WriteVecShift, FPC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteVecLogic, FPC_RSV01, 1>;
|
||||
defm : SMWriteResPair<WriteVecALU, FPC_RSV01, 1>;
|
||||
defm : SMWriteResPair<WriteVecIMul, FPC_RSV0, 4>;
|
||||
defm : SMWriteResPair<WriteShuffle, FPC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteBlend, FPC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteMPSAD, FPC_RSV0, 7>;
|
||||
|
||||
// String instructions.
|
||||
// Packed Compare Implicit Length Strings, Return Mask
|
||||
def : WriteRes<WritePCmpIStrM, [FPC_RSV0]> {
|
||||
let Latency = 13;
|
||||
let ResourceCycles = [13];
|
||||
}
|
||||
def : WriteRes<WritePCmpIStrMLd, [FPC_RSV0, MEC_RSV]> {
|
||||
let Latency = 13;
|
||||
let ResourceCycles = [13, 1];
|
||||
}
|
||||
|
||||
// Packed Compare Explicit Length Strings, Return Mask
|
||||
def : WriteRes<WritePCmpEStrM, [FPC_RSV0]> {
|
||||
let Latency = 17;
|
||||
let ResourceCycles = [17];
|
||||
}
|
||||
def : WriteRes<WritePCmpEStrMLd, [FPC_RSV0, MEC_RSV]> {
|
||||
let Latency = 17;
|
||||
let ResourceCycles = [17, 1];
|
||||
}
|
||||
|
||||
// Packed Compare Implicit Length Strings, Return Index
|
||||
def : WriteRes<WritePCmpIStrI, [FPC_RSV0]> {
|
||||
let Latency = 17;
|
||||
let ResourceCycles = [17];
|
||||
}
|
||||
def : WriteRes<WritePCmpIStrILd, [FPC_RSV0, MEC_RSV]> {
|
||||
let Latency = 17;
|
||||
let ResourceCycles = [17, 1];
|
||||
}
|
||||
|
||||
// Packed Compare Explicit Length Strings, Return Index
|
||||
def : WriteRes<WritePCmpEStrI, [FPC_RSV0]> {
|
||||
let Latency = 21;
|
||||
let ResourceCycles = [21];
|
||||
}
|
||||
def : WriteRes<WritePCmpEStrILd, [FPC_RSV0, MEC_RSV]> {
|
||||
let Latency = 21;
|
||||
let ResourceCycles = [21, 1];
|
||||
}
|
||||
|
||||
// AES Instructions.
|
||||
def : WriteRes<WriteAESDecEnc, [FPC_RSV0]> {
|
||||
let Latency = 8;
|
||||
let ResourceCycles = [5];
|
||||
}
|
||||
def : WriteRes<WriteAESDecEncLd, [FPC_RSV0, MEC_RSV]> {
|
||||
let Latency = 8;
|
||||
let ResourceCycles = [5, 1];
|
||||
}
|
||||
|
||||
def : WriteRes<WriteAESIMC, [FPC_RSV0]> {
|
||||
let Latency = 8;
|
||||
let ResourceCycles = [5];
|
||||
}
|
||||
def : WriteRes<WriteAESIMCLd, [FPC_RSV0, MEC_RSV]> {
|
||||
let Latency = 8;
|
||||
let ResourceCycles = [5, 1];
|
||||
}
|
||||
|
||||
def : WriteRes<WriteAESKeyGen, [FPC_RSV0]> {
|
||||
let Latency = 8;
|
||||
let ResourceCycles = [5];
|
||||
}
|
||||
def : WriteRes<WriteAESKeyGenLd, [FPC_RSV0, MEC_RSV]> {
|
||||
let Latency = 8;
|
||||
let ResourceCycles = [5, 1];
|
||||
}
|
||||
|
||||
// Carry-less multiplication instructions.
|
||||
def : WriteRes<WriteCLMul, [FPC_RSV0]> {
|
||||
let Latency = 10;
|
||||
let ResourceCycles = [10];
|
||||
}
|
||||
def : WriteRes<WriteCLMulLd, [FPC_RSV0, MEC_RSV]> {
|
||||
let Latency = 10;
|
||||
let ResourceCycles = [10, 1];
|
||||
}
|
||||
|
||||
|
||||
def : WriteRes<WriteSystem, [FPC_RSV0]> { let Latency = 100; }
|
||||
def : WriteRes<WriteMicrocoded, [FPC_RSV0]> { let Latency = 100; }
|
||||
def : WriteRes<WriteFence, [MEC_RSV]>;
|
||||
def : WriteRes<WriteNop, []>;
|
||||
|
||||
// AVX is not supported on that architecture, but we should define the basic
|
||||
// scheduling resources anyway.
|
||||
def : WriteRes<WriteIMulH, [FPC_RSV0]>;
|
||||
defm : SMWriteResPair<WriteVarBlend, FPC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteFVarBlend, FPC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteFShuffle256, FPC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteShuffle256, FPC_RSV0, 1>;
|
||||
defm : SMWriteResPair<WriteVarVecShift, FPC_RSV0, 1>;
|
||||
} // SchedModel
|
||||
|
||||
Loading…
Reference in New Issue
Block a user