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Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move

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a convert pattern close to the instruction definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136320 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-07-28 01:26:39 +00:00
parent b2e7c8250b
commit 2e64ae4101
3 changed files with 27 additions and 7 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
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@ -964,6 +964,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
setOperationAction(ISD::FNEG, MVT::v4f64, Custom); setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
// Custom lower several nodes for 256-bit types. // Custom lower several nodes for 256-bit types.
for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {

17
lib/Target/X86/X86InstrSSE.td
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@ -884,7 +884,6 @@ def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
[(set VR128:$dst, [(set VR128:$dst,
(int_x86_sse2_cvttps2dq (memop addr:$src)))]>; (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"vcvttps2dq\t{$src, $dst|$dst, $src}", "vcvttps2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, [(set VR128:$dst,
@ -896,6 +895,16 @@ def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
(memop addr:$src)))]>, (memop addr:$src)))]>,
XS, VEX, Requires<[HasAVX]>; XS, VEX, Requires<[HasAVX]>;
def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
(Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
(CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
(VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
(VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src), (ins VR128:$src),
"cvttpd2dq\t{$src, $dst|$dst, $src}", "cvttpd2dq\t{$src, $dst|$dst, $src}",
@ -3857,12 +3866,6 @@ def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>; (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
// vector -> vector casts
def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
(Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
(CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
// Use movaps / movups for SSE integer load / store (one byte shorter). // Use movaps / movups for SSE integer load / store (one byte shorter).
// The instructions selected below are then converted to MOVDQA/MOVDQU // The instructions selected below are then converted to MOVDQA/MOVDQU
// during the SSE domain pass. // during the SSE domain pass.

14
test/CodeGen/X86/avx-256-cvt.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
; CHECK: vcvtdq2ps %ymm
define <8 x float> @funcA(<8 x i32> %a) nounwind {
%b = sitofp <8 x i32> %a to <8 x float>
ret <8 x float> %b
}
; CHECK: vcvttps2dq %ymm
define <8 x i32> @funcB(<8 x float> %a) nounwind {
%b = fptosi <8 x float> %a to <8 x i32>
ret <8 x i32> %b
}