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Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move
a convert pattern close to the instruction definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136320 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -964,6 +964,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
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setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
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setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
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setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
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// Custom lower several nodes for 256-bit types.
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// Custom lower several nodes for 256-bit types.
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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@ -884,7 +884,6 @@ def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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[(set VR128:$dst,
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
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(int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
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def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvttps2dq\t{$src, $dst|$dst, $src}",
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"vcvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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@ -896,6 +895,16 @@ def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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(memop addr:$src)))]>,
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(memop addr:$src)))]>,
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XS, VEX, Requires<[HasAVX]>;
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XS, VEX, Requires<[HasAVX]>;
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def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
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(Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
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def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
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(CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
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def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
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(VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
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def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
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(VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
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def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
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def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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(ins VR128:$src),
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"cvttpd2dq\t{$src, $dst|$dst, $src}",
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"cvttpd2dq\t{$src, $dst|$dst, $src}",
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@ -3857,12 +3866,6 @@ def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
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def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
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def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
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(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
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(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
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// vector -> vector casts
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def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
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(Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
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def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
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(CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
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// Use movaps / movups for SSE integer load / store (one byte shorter).
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// Use movaps / movups for SSE integer load / store (one byte shorter).
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// The instructions selected below are then converted to MOVDQA/MOVDQU
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// The instructions selected below are then converted to MOVDQA/MOVDQU
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// during the SSE domain pass.
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// during the SSE domain pass.
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14
test/CodeGen/X86/avx-256-cvt.ll
Normal file
14
test/CodeGen/X86/avx-256-cvt.ll
Normal file
@ -0,0 +1,14 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: vcvtdq2ps %ymm
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define <8 x float> @funcA(<8 x i32> %a) nounwind {
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%b = sitofp <8 x i32> %a to <8 x float>
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ret <8 x float> %b
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}
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; CHECK: vcvttps2dq %ymm
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define <8 x i32> @funcB(<8 x float> %a) nounwind {
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%b = fptosi <8 x float> %a to <8 x i32>
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ret <8 x i32> %b
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}
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