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R600/SI: Remove VOP2_REV definitions from target-specific instructions
The getCommute* functions are only used with pseudos, so this commit doesn't change anything. The issue with missing non-rev versions of shift instructions on VI will fixed separately. Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227989 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Marek Olsak
parent
5e58a1bc29
commit
2ea95bd471
@ -849,25 +849,22 @@ class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
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}
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multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
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string opName, string revOpSI> {
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string opName, string revOp> {
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def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
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VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
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VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
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def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
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VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
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SIMCInstr <opName#"_e32", SISubtarget.SI>;
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}
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multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
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string opName, string revOpSI, string revOpVI> {
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string opName, string revOp> {
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def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
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VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
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VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
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def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
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VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
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SIMCInstr <opName#"_e32", SISubtarget.SI>;
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def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
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VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
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SIMCInstr <opName#"_e32", SISubtarget.VI>;
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}
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@ -941,20 +938,18 @@ multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
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}
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multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
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list<dag> pattern, string opName, string revOpSI, string revOpVI,
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list<dag> pattern, string opName, string revOp,
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bit HasMods = 1, bit UseFullOp = 0> {
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def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
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VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>;
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VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
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def _si : VOP3_Real_si <op.SI3,
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outs, ins, asm, opName>,
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VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
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VOP3DisableFields<1, 0, HasMods>;
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def _vi : VOP3_Real_vi <op.VI3,
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outs, ins, asm, opName>,
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VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
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VOP3DisableFields<1, 0, HasMods>;
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}
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@ -970,14 +965,12 @@ multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
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let sdst = SIOperand.VCC, Defs = [VCC] in {
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def _si : VOP3b <op.SI3, outs, ins, asm, []>,
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VOP3DisableFields<1, 0, HasMods>,
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SIMCInstr<opName#"_e64", SISubtarget.SI>,
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VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
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SIMCInstr<opName#"_e64", SISubtarget.SI>;
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// TODO: Do we need this VI variant here?
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/*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, []>,
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VOP3DisableFields<1, 0, HasMods>,
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SIMCInstr<opName#"_e64", SISubtarget.VI>,
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VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
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SIMCInstr<opName#"_e64", SISubtarget.VI>;*/
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} // End sdst = SIOperand.VCC, Defs = [VCC]
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}
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@ -1056,17 +1049,17 @@ multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
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multiclass VOP2_Helper <vop2 op, string opName, dag outs,
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dag ins32, string asm32, list<dag> pat32,
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dag ins64, string asm64, list<dag> pat64,
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string revOpSI, string revOpVI, bit HasMods> {
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defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>;
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string revOp, bit HasMods> {
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defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
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defm _e64 : VOP3_2_m <op,
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outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods
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outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
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>;
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}
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multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
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SDPatternOperator node = null_frag,
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string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper <
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string revOp = opName> : VOP2_Helper <
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op, opName, P.Outs,
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P.Ins32, P.Asm32, [],
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P.Ins64, P.Asm64,
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@ -1076,7 +1069,7 @@ multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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revOpSI, revOpVI, P.HasModifiers
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revOp, P.HasModifiers
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>;
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multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
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@ -1084,7 +1077,7 @@ multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
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dag ins64, string asm64, list<dag> pat64,
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string revOp, bit HasMods> {
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defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>;
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defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
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defm _e64 : VOP3b_2_m <op,
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outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
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@ -1110,16 +1103,16 @@ multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
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multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
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dag ins32, string asm32, list<dag> pat32,
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dag ins64, string asm64, list<dag> pat64,
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string revOpSI, string revOpVI, bit HasMods> {
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defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOpSI>;
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string revOp, bit HasMods> {
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defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
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defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
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revOpSI, revOpVI, HasMods>;
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revOp, HasMods>;
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}
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multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
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SDPatternOperator node = null_frag,
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string revOpSI = opName, string revOpVI = revOpSI>
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string revOp = opName>
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: VOP2_VI3_Helper <
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op, opName, P.Outs,
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P.Ins32, P.Asm32, [],
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@ -1130,7 +1123,7 @@ multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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revOpSI, revOpVI, P.HasModifiers
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revOp, P.HasModifiers
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>;
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class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
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@ -1457,22 +1457,19 @@ defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32,
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AMDGPUumax
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>;
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// No non-Rev Op on VI
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defm V_LSHRREV_B32 : VOP2Inst <
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vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
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"v_lshr_b32", "v_lshrrev_b32"
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"v_lshr_b32"
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>;
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// No non-Rev OP on VI
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defm V_ASHRREV_I32 : VOP2Inst <
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vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
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"v_ashr_i32", "v_ashrrev_i32"
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"v_ashr_i32"
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>;
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// No non-Rev OP on VI
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defm V_LSHLREV_B32 : VOP2Inst <
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vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
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"v_lshl_b32", "v_lshlrev_b32"
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"v_lshl_b32"
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>;
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defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32",
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