6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-16 11:30:51 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Remove VOP2_REV definitions from target-specific instructions

Browse Source 
The getCommute* functions are only used with pseudos, so this commit doesn't
change anything.

The issue with missing non-rev versions of shift instructions on VI will fixed
separately.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227989 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Marek Olsak 2015-02-03 17:38:05 +00:00
parent 5e58a1bc29
commit 2ea95bd471
2 changed files with 22 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
lib/Target/R600/SIInstrInfo.td
View File

@ -849,25 +849,22 @@ class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
} }
multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern, multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
string opName, string revOpSI> { string opName, string revOp> {
def "" : VOP2_Pseudo <outs, ins, pattern, opName>, def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>; VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
def _si : VOP2 <op.SI, outs, ins, opName#asm, []>, def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
SIMCInstr <opName#"_e32", SISubtarget.SI>; SIMCInstr <opName#"_e32", SISubtarget.SI>;
} }
multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern, multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
string opName, string revOpSI, string revOpVI> { string opName, string revOp> {
def "" : VOP2_Pseudo <outs, ins, pattern, opName>, def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>; VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
def _si : VOP2 <op.SI, outs, ins, opName#asm, []>, def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
SIMCInstr <opName#"_e32", SISubtarget.SI>; SIMCInstr <opName#"_e32", SISubtarget.SI>;
def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>, def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
SIMCInstr <opName#"_e32", SISubtarget.VI>; SIMCInstr <opName#"_e32", SISubtarget.VI>;
} }
@ -941,20 +938,18 @@ multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
} }
multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm, multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
list<dag> pattern, string opName, string revOpSI, string revOpVI, list<dag> pattern, string opName, string revOp,
bit HasMods = 1, bit UseFullOp = 0> { bit HasMods = 1, bit UseFullOp = 0> {
def "" : VOP3_Pseudo <outs, ins, pattern, opName>, def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>; VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
def _si : VOP3_Real_si <op.SI3, def _si : VOP3_Real_si <op.SI3,
outs, ins, asm, opName>, outs, ins, asm, opName>,
VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
VOP3DisableFields<1, 0, HasMods>; VOP3DisableFields<1, 0, HasMods>;
def _vi : VOP3_Real_vi <op.VI3, def _vi : VOP3_Real_vi <op.VI3,
outs, ins, asm, opName>, outs, ins, asm, opName>,
VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
VOP3DisableFields<1, 0, HasMods>; VOP3DisableFields<1, 0, HasMods>;
} }
@ -970,14 +965,12 @@ multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
let sdst = SIOperand.VCC, Defs = [VCC] in { let sdst = SIOperand.VCC, Defs = [VCC] in {
def _si : VOP3b <op.SI3, outs, ins, asm, []>, def _si : VOP3b <op.SI3, outs, ins, asm, []>,
VOP3DisableFields<1, 0, HasMods>, VOP3DisableFields<1, 0, HasMods>,
SIMCInstr<opName#"_e64", SISubtarget.SI>, SIMCInstr<opName#"_e64", SISubtarget.SI>;
VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
// TODO: Do we need this VI variant here? // TODO: Do we need this VI variant here?
/*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, []>, /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, []>,
VOP3DisableFields<1, 0, HasMods>, VOP3DisableFields<1, 0, HasMods>,
SIMCInstr<opName#"_e64", SISubtarget.VI>, SIMCInstr<opName#"_e64", SISubtarget.VI>;*/
VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
} // End sdst = SIOperand.VCC, Defs = [VCC] } // End sdst = SIOperand.VCC, Defs = [VCC]
} }
@ -1056,17 +1049,17 @@ multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
multiclass VOP2_Helper <vop2 op, string opName, dag outs, multiclass VOP2_Helper <vop2 op, string opName, dag outs,
dag ins32, string asm32, list<dag> pat32, dag ins32, string asm32, list<dag> pat32,
dag ins64, string asm64, list<dag> pat64, dag ins64, string asm64, list<dag> pat64,
string revOpSI, string revOpVI, bit HasMods> { string revOp, bit HasMods> {
defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>; defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
defm _e64 : VOP3_2_m <op, defm _e64 : VOP3_2_m <op,
outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
>; >;
} }
multiclass VOP2Inst <vop2 op, string opName, VOPProfile P, multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
SDPatternOperator node = null_frag, SDPatternOperator node = null_frag,
string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper < string revOp = opName> : VOP2_Helper <
op, opName, P.Outs, op, opName, P.Outs,
P.Ins32, P.Asm32, [], P.Ins32, P.Asm32, [],
P.Ins64, P.Asm64, P.Ins64, P.Asm64,
@ -1076,7 +1069,7 @@ multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
i1:$clamp, i32:$omod)), i1:$clamp, i32:$omod)),
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
revOpSI, revOpVI, P.HasModifiers revOp, P.HasModifiers
>; >;
multiclass VOP2b_Helper <vop2 op, string opName, dag outs, multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
@ -1084,7 +1077,7 @@ multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
dag ins64, string asm64, list<dag> pat64, dag ins64, string asm64, list<dag> pat64,
string revOp, bit HasMods> { string revOp, bit HasMods> {
defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>; defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
defm _e64 : VOP3b_2_m <op, defm _e64 : VOP3b_2_m <op,
outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
@ -1110,16 +1103,16 @@ multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs, multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
dag ins32, string asm32, list<dag> pat32, dag ins32, string asm32, list<dag> pat32,
dag ins64, string asm64, list<dag> pat64, dag ins64, string asm64, list<dag> pat64,
string revOpSI, string revOpVI, bit HasMods> { string revOp, bit HasMods> {
defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOpSI>; defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
revOpSI, revOpVI, HasMods>; revOp, HasMods>;
} }
multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P, multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
SDPatternOperator node = null_frag, SDPatternOperator node = null_frag,
string revOpSI = opName, string revOpVI = revOpSI> string revOp = opName>
: VOP2_VI3_Helper < : VOP2_VI3_Helper <
op, opName, P.Outs, op, opName, P.Outs,
P.Ins32, P.Asm32, [], P.Ins32, P.Asm32, [],
@ -1130,7 +1123,7 @@ multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
i1:$clamp, i32:$omod)), i1:$clamp, i32:$omod)),
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
revOpSI, revOpVI, P.HasModifiers revOp, P.HasModifiers
>; >;
class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :

9
lib/Target/R600/SIInstructions.td
View File

@ -1457,22 +1457,19 @@ defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32,
AMDGPUumax AMDGPUumax
>; >;
// No non-Rev Op on VI
defm V_LSHRREV_B32 : VOP2Inst < defm V_LSHRREV_B32 : VOP2Inst <
vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
"v_lshr_b32", "v_lshrrev_b32" "v_lshr_b32"
>; >;
// No non-Rev OP on VI
defm V_ASHRREV_I32 : VOP2Inst < defm V_ASHRREV_I32 : VOP2Inst <
vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
"v_ashr_i32", "v_ashrrev_i32" "v_ashr_i32"
>; >;
// No non-Rev OP on VI
defm V_LSHLREV_B32 : VOP2Inst < defm V_LSHLREV_B32 : VOP2Inst <
vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
"v_lshl_b32", "v_lshlrev_b32" "v_lshl_b32"
>; >;
defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32",