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Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185999 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -490,6 +490,34 @@ class TEQ_FM<bits<6> funct> {
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let Inst{5-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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// System calls format <op|code_|funct>
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//===----------------------------------------------------------------------===//
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class SYS_FM<bits<6> funct>
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{
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bits<20> code_;
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bits<32> Inst;
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let Inst{31-26} = 0x0;
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let Inst{25-6} = code_;
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let Inst{5-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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// Break instruction format <op|code_1|funct>
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//===----------------------------------------------------------------------===//
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class BRK_FM<bits<6> funct>
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{
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bits<10> code_1;
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bits<10> code_2;
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bits<32> Inst;
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let Inst{31-26} = 0x0;
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let Inst{25-16} = code_1;
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let Inst{15-6} = code_2;
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let Inst{5-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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//
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// FLOATING POINT INSTRUCTION FORMATS
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@ -250,6 +250,12 @@ def simm16 : Operand<i32> {
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def simm20 : Operand<i32> {
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}
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def uimm20 : Operand<i32> {
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}
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def uimm10 : Operand<i32> {
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}
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def simm16_64 : Operand<i64>;
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def shamt : Operand<i32>;
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@ -637,6 +643,14 @@ class BAL_FT :
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let hasDelaySlot = 1;
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let Defs = [RA];
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}
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// Syscall
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class SYS_FT<string opstr> :
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InstSE<(outs), (ins uimm20:$code_),
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!strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
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// Break
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class BRK_FT<string opstr> :
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InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
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!strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
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// Sync
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let hasSideEffects = 1 in
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@ -941,6 +955,9 @@ defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
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def SYNC : SYNC_FT, SYNC_FM;
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def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>;
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def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
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def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
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/// Load-linked, Store-conditional
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let Predicates = [NotN64, HasStdEnc] in {
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def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
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@ -1119,6 +1136,10 @@ def : InstAlias<"bnez $rs,$offset",
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def : InstAlias<"beqz $rs,$offset",
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(BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
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Requires<[NotMips64]>;
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def : InstAlias<"syscall", (SYSCALL 0), 1>;
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def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
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def : InstAlias<"break", (BREAK 0, 0), 1>;
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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@ -39,7 +39,17 @@ $JTI0_0:
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.set FPU_MASK,$f7
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.set r3,$3
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.set f6,$f6
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#CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
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#CHECK: and $3, $15, $15 # encoding: [0x01,0xef,0x18,0x24]
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# CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
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# CHECK: and $3, $15, $15 # encoding: [0x01,0xef,0x18,0x24]
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# CHECK: break # encoding: [0x00,0x00,0x00,0x0d]
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# CHECK: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
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# CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
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# CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
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# CHECK: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c]
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abs.s f6,FPU_MASK
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and r3,$t7,STORE_MASK
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break
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break 7
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break 7,5
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syscall
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syscall 0x3454
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