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[X86][SSE] Use (V)PINSRB for direct byte insertion in 16i8 buildvector on SSE4.1 targets
This patch allows SSE4.1 targets to use (V)PINSRB to create 16i8 vectors by inserting i8 scalars directly into a XMM register instead of merging pairs of i8 scalars into a i16 and using the SSE2 PINSRW instruction. This allows folding of byte loads and reduces scalar register usage as well. Differential Revision: http://reviews.llvm.org/D8839 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234193 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -4460,6 +4460,29 @@ static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
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SDLoc dl(Op);
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SDLoc dl(Op);
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SDValue V;
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SDValue V;
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bool First = true;
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bool First = true;
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// SSE4.1 - use PINSRB to insert each byte directly.
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if (Subtarget->hasSSE41()) {
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for (unsigned i = 0; i < 16; ++i) {
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bool isNonZero = (NonZeros & (1 << i)) != 0;
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if (isNonZero) {
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if (First) {
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if (NumZero)
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V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
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else
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V = DAG.getUNDEF(MVT::v16i8);
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First = false;
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}
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V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
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MVT::v16i8, V, Op.getOperand(i),
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DAG.getIntPtrConstant(i));
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}
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}
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return V;
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}
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// Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
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for (unsigned i = 0; i < 16; ++i) {
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for (unsigned i = 0; i < 16; ++i) {
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bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
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bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
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if (ThisIsNonZero && First) {
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if (ThisIsNonZero && First) {
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@ -100,37 +100,29 @@ define <8 x i8> @foo3_8(<8 x float> %src) {
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;
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;
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; CHECK-WIDE-LABEL: foo3_8:
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; CHECK-WIDE-LABEL: foo3_8:
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; CHECK-WIDE: ## BB#0:
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; CHECK-WIDE: ## BB#0:
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; CHECK-WIDE-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
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; CHECK-WIDE-NEXT: vpinsrb $0, %eax, %xmm0, %xmm1
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; CHECK-WIDE-NEXT: shll $8, %eax
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; CHECK-WIDE-NEXT: vmovshdup %xmm0, %xmm2 ## xmm2 = xmm0[1,1,3,3]
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; CHECK-WIDE-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %ecx
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; CHECK-WIDE-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: movzbl %cl, %ecx
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; CHECK-WIDE-NEXT: vpermilpd $1, %xmm0, %xmm2 ## xmm2 = xmm0[1,0]
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; CHECK-WIDE-NEXT: orl %eax, %ecx
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
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; CHECK-WIDE-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
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; CHECK-WIDE-NEXT: vpermilps $231, %xmm0, %xmm2 ## xmm2 = xmm0[3,1,2,3]
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; CHECK-WIDE-NEXT: shll $8, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %edx
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; CHECK-WIDE-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: movzbl %dl, %edx
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; CHECK-WIDE-NEXT: orl %eax, %edx
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; CHECK-WIDE-NEXT: vpinsrw $0, %edx, %xmm0, %xmm1
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; CHECK-WIDE-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-WIDE-NEXT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-WIDE-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax
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; CHECK-WIDE-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vmovshdup %xmm0, %xmm2 ## xmm2 = xmm0[1,1,3,3]
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: shll $8, %eax
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; CHECK-WIDE-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %ecx
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; CHECK-WIDE-NEXT: vpermilpd $1, %xmm0, %xmm2 ## xmm2 = xmm0[1,0]
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; CHECK-WIDE-NEXT: movzbl %cl, %ecx
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; CHECK-WIDE-NEXT: orl %eax, %ecx
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; CHECK-WIDE-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,1,2,3]
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: shll $8, %eax
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; CHECK-WIDE-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
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; CHECK-WIDE-NEXT: vpermilps $231, %xmm0, %xmm0 ## xmm0 = xmm0[3,1,2,3]
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %ecx
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax
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; CHECK-WIDE-NEXT: movzbl %cl, %ecx
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; CHECK-WIDE-NEXT: vpinsrb $7, %eax, %xmm1, %xmm0
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; CHECK-WIDE-NEXT: orl %eax, %ecx
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; CHECK-WIDE-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm0
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; CHECK-WIDE-NEXT: vzeroupper
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; CHECK-WIDE-NEXT: vzeroupper
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; CHECK-WIDE-NEXT: retl
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; CHECK-WIDE-NEXT: retl
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%res = fptosi <8 x float> %src to <8 x i8>
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%res = fptosi <8 x float> %src to <8 x i8>
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@ -145,21 +137,17 @@ define <4 x i8> @foo3_4(<4 x float> %src) {
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;
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;
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; CHECK-WIDE-LABEL: foo3_4:
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; CHECK-WIDE-LABEL: foo3_4:
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; CHECK-WIDE: ## BB#0:
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; CHECK-WIDE: ## BB#0:
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; CHECK-WIDE-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
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; CHECK-WIDE-NEXT: vpinsrb $0, %eax, %xmm0, %xmm1
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; CHECK-WIDE-NEXT: shll $8, %eax
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; CHECK-WIDE-NEXT: vmovshdup %xmm0, %xmm2 ## xmm2 = xmm0[1,1,3,3]
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; CHECK-WIDE-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %ecx
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; CHECK-WIDE-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: movzbl %cl, %ecx
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; CHECK-WIDE-NEXT: vpermilpd $1, %xmm0, %xmm2 ## xmm2 = xmm0[1,0]
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; CHECK-WIDE-NEXT: orl %eax, %ecx
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; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax
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; CHECK-WIDE-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
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; CHECK-WIDE-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
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; CHECK-WIDE-NEXT: vpermilps $231, %xmm0, %xmm0 ## xmm0 = xmm0[3,1,2,3]
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; CHECK-WIDE-NEXT: shll $8, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax
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; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %edx
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; CHECK-WIDE-NEXT: vpinsrb $3, %eax, %xmm1, %xmm0
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; CHECK-WIDE-NEXT: movzbl %dl, %edx
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; CHECK-WIDE-NEXT: orl %eax, %edx
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; CHECK-WIDE-NEXT: vpinsrw $0, %edx, %xmm0, %xmm0
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; CHECK-WIDE-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0
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; CHECK-WIDE-NEXT: retl
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; CHECK-WIDE-NEXT: retl
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%res = fptosi <4 x float> %src to <4 x i8>
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%res = fptosi <4 x float> %src to <4 x i8>
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ret <4 x i8> %res
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ret <4 x i8> %res
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@ -651,18 +651,30 @@ define <16 x i8> @shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(
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}
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}
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define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(i8 %i) {
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define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(i8 %i) {
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; SSE-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSE2-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSE: # BB#0:
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; SSE2: # BB#0:
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; SSE-NEXT: shll $8, %edi
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; SSE2-NEXT: shll $8, %edi
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; SSE-NEXT: pxor %xmm0, %xmm0
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; SSE2-NEXT: pxor %xmm0, %xmm0
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; SSE-NEXT: pinsrw $2, %edi, %xmm0
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; SSE2-NEXT: pinsrw $2, %edi, %xmm0
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; SSE-NEXT: retq
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shll $8, %edi
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; SSSE3-NEXT: pxor %xmm0, %xmm0
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; SSSE3-NEXT: pinsrw $2, %edi, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSE41: # BB#0:
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; SSE41-NEXT: pxor %xmm0, %xmm0
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; SSE41-NEXT: pinsrb $5, %edi, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; AVX: # BB#0:
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; AVX: # BB#0:
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; AVX-NEXT: shll $8, %edi
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; AVX-NEXT: vpxor %xmm0, %xmm0
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; AVX-NEXT: vpxor %xmm0, %xmm0
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; AVX-NEXT: vpinsrw $2, %edi, %xmm0
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; AVX-NEXT: vpinsrb $5, %edi, %xmm0
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; AVX-NEXT: retq
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; AVX-NEXT: retq
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%a = insertelement <16 x i8> undef, i8 %i, i32 0
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%a = insertelement <16 x i8> undef, i8 %i, i32 0
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%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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@ -670,18 +682,30 @@ define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(
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}
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}
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define <16 x i8> @shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16(i8 %i) {
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define <16 x i8> @shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16(i8 %i) {
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; SSE-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
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; SSE2-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
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; SSE: # BB#0:
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; SSE2: # BB#0:
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; SSE-NEXT: shll $8, %edi
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; SSE2-NEXT: shll $8, %edi
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; SSE-NEXT: pxor %xmm0, %xmm0
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; SSE2-NEXT: pxor %xmm0, %xmm0
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; SSE-NEXT: pinsrw $7, %edi, %xmm0
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; SSE2-NEXT: pinsrw $7, %edi, %xmm0
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; SSE-NEXT: retq
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shll $8, %edi
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; SSSE3-NEXT: pxor %xmm0, %xmm0
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; SSSE3-NEXT: pinsrw $7, %edi, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
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; SSE41: # BB#0:
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; SSE41-NEXT: pxor %xmm0, %xmm0
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; SSE41-NEXT: pinsrb $15, %edi, %xmm0
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; SSE41-NEXT: retq
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;
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;
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; AVX-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
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; AVX-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
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; AVX: # BB#0:
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; AVX: # BB#0:
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; AVX-NEXT: shll $8, %edi
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; AVX-NEXT: vpxor %xmm0, %xmm0
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; AVX-NEXT: vpxor %xmm0, %xmm0
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; AVX-NEXT: vpinsrw $7, %edi, %xmm0
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; AVX-NEXT: vpinsrb $15, %edi, %xmm0
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; AVX-NEXT: retq
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; AVX-NEXT: retq
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%a = insertelement <16 x i8> undef, i8 %i, i32 0
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%a = insertelement <16 x i8> undef, i8 %i, i32 0
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%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 16>
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%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 16>
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@ -689,18 +713,30 @@ define <16 x i8> @shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16(
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}
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}
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define <16 x i8> @shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(i8 %i) {
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define <16 x i8> @shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(i8 %i) {
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; SSE-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSE2-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSE: # BB#0:
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; SSE2: # BB#0:
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; SSE-NEXT: movzbl %dil, %eax
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; SSE2-NEXT: movzbl %dil, %eax
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; SSE-NEXT: pxor %xmm0, %xmm0
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; SSE2-NEXT: pxor %xmm0, %xmm0
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; SSE-NEXT: pinsrw $1, %eax, %xmm0
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; SSE2-NEXT: pinsrw $1, %eax, %xmm0
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; SSE-NEXT: retq
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movzbl %dil, %eax
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; SSSE3-NEXT: pxor %xmm0, %xmm0
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; SSSE3-NEXT: pinsrw $1, %eax, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; SSE41: # BB#0:
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; SSE41-NEXT: pxor %xmm0, %xmm0
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; SSE41-NEXT: pinsrb $2, %edi, %xmm0
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; SSE41-NEXT: retq
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;
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;
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; AVX-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; AVX-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; AVX: # BB#0:
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; AVX: # BB#0:
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; AVX-NEXT: movzbl %dil, %eax
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; AVX-NEXT: vpxor %xmm0, %xmm0
|
; AVX-NEXT: vpxor %xmm0, %xmm0
|
||||||
; AVX-NEXT: vpinsrw $1, %eax, %xmm0
|
; AVX-NEXT: vpinsrb $2, %edi, %xmm0
|
||||||
; AVX-NEXT: retq
|
; AVX-NEXT: retq
|
||||||
%a = insertelement <16 x i8> undef, i8 %i, i32 3
|
%a = insertelement <16 x i8> undef, i8 %i, i32 3
|
||||||
%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 19, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 19, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||||
|
Loading…
Reference in New Issue
Block a user