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optimize, mc, x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145200 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -872,8 +872,8 @@ be used to verify some algorithms.
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<li>LLVM now includes a pass to optimize retain/release calls for the
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<a href="http://clang.llvm.org/docs/AutomaticReferenceCounting.html">Automatic
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Reference Counting</a> (ARC) Objective-C language feature (in
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lib/Transforms/ObjCARC). It is a decent example of implementing a
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source-language-specific optimization in LLVM.</li>
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lib/Transforms/Scalar/ObjCARC.cpp). It is a decent example of implementing
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a source-language-specific optimization in LLVM.</li>
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</ul>
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@ -889,35 +889,32 @@ be used to verify some algorithms.
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<p>The LLVM Machine Code (aka MC) subsystem was created to solve a number of
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problems in the realm of assembly, disassembly, object file format handling,
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and a number of other related areas that CPU instruction-set level tools work
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in.</p>
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in. For more information, please see
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the <a href="http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html">Intro
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to the LLVM MC Project Blog Post</a>.</p>
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<ul>
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<li>The ELF object streamers are much more full featured.</li>
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<li>Target dependent relocation handling has been refactored into the Targets.</li>
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<li>Early stage MC-JIT infrastructure has been implemented.</li>
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<li>The MC layer has undergone significant refactoring to eliminate layering
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violations that caused it to pull in the LLVM compiler backend code.</li>
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<li>The ELF object file writers are much more full featured.</li>
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<li>The integrated assembler now supports #line directives.</li>
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<li>An early implementation of a JIT built on top of the MC framework (known
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as MC-JIT) has been implemented and will eventually replace the old JIT.
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It emits object files direct to memory and uses a runtime dynamic linker to
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resolve references and drive lazy compilation. The MC-JIT enables much
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greater code reuse between the JIT and the static compiler and provides
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better integration with the platform ABI as a result.
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</li>
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<li>The assembly printer now makes uses of assemblers instruction aliases
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(InstAliases) to print simplified mneumonics when possible.</li>
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<li>TableGen can now autogenerate MC expansion logic for pseudo
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instructions that expand to multiple MC instructions (through the
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PseudoInstExpansion class).</li>
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<li>XXX: llvm-objdump / dwarf parser library / llvm-dwarfdump (d0k)
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object file parsing stuff and llvm-size (mspencer). Status?</li>
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</ul>
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<p>The MC-JIT is a major new feature for MC, and will eventually grow to replace
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the current JIT implementation. It emits object files direct to memory and
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uses a runtime dynamic linker to resolve references and drive lazy compilation.
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The MC-JIT enables much greater code reuse between the JIT and the static
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compiler and provides better integration with the platform ABI as a result.</p>
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<p>For more information, please see
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the <a href="http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html">Intro
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to the LLVM MC Project Blog Post</a>.</p>
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InstAliases now automatically used in the asmprinter where they are shorter.
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Table generated MC expansion logic for pseudo instructions that expand to multiple MC instructions through the PseudoInstExpansion class. (JimG)
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#line directives in integrated assembler
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llvm-rtdyld: JimG
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llvm-objdump / dwarf parser library / llvm-dwarfdump (d0k)
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object file parsing stuff and llvm-size (mspencer)
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</div>
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<!--=========================================================================-->
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@ -932,20 +929,17 @@ compiler and provides better integration with the platform ABI as a result.</p>
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make it run faster:</p>
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<ul>
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better performance for indirect gotos through new tail dup pass.
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<li>LLVM generates substantially better code for indirect gotos due to a new
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tail duplication pass, which can be a substantial performance win for
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interpreter loops that use them.</li>
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<li>Exception handling and debug information is now emitted with CFI directives,
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yielding <a href="http://blog.mozilla.com/respindola/2011/05/12/cfi-directives/">much smaller executables</a> for some C++ applications.
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</li>
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Codegen now supports vector "select" operations on vector comparisons, turning
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them into various optimized code sequences (e.g. using the SSE4/AVX "blend"
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instructions).
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EH and debug information produced with CFI directives, yielding smaller executables: http://blog.mozilla.com/respindola/2011/05/12/cfi-directives/
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Domain fixing pass is now target independent (ExecutionDepsFix pass). (Jakob)
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<!--
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<li></li>
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-->
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<li>The code generator now supports vector "select" operations on vector
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comparisons, turning them into various optimized code sequences (e.g.
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using the SSE4/AVX "blend" instructions).</li>
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<li>XXX: Domain fixing pass is now target independent (ExecutionDepsFix pass). (Jakob)</li>
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</ul>
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</div>
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@ -959,29 +953,30 @@ compiler and provides better integration with the platform ABI as a result.</p>
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<p>New features and major changes in the X86 target include:</p>
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<ul>
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<li>The X86 backend, assembler and disassembler now completely support AVX.
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To enable it pass <code>-mavx</code> to the compiler.</li>
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<li>The X86 backend now supports
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all <a href="http://llvm.org/PR879">inline assembly that uses the X86
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floating point stack</a>.</li>
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<li>The CRC32 intrinsics have been renamed. The intrinsics were previously
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<code>@llvm.x86.sse42.crc32.[8|16|32]</code>
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and <code>@llvm.x86.sse42.crc64.[8|64]</code>. They have been renamed to
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<code>@llvm.x86.sse42.crc32.32.[8|16|32]</code> and
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<code>@llvm.x86.sse42.crc32.64.[8|64]</code>.</li>
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X86: inline assembler supports .code32 and .code64.
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AVX support, assembler, compiler and disassembler.
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X86 backend support for NaCl (David Meyer / Nick L)
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SSE domain fixing code enabled for AVX (Bruno/Jakob).
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X86 backend synthesizes horizontal add/sub instructions from generic code.
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X86: Tons of encoding improvements and new instructions (e.g. Atom, Ivy Bridge,
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and BMI instructions)
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added to assembler and disassembler (Craig Topper)
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X86-64 generates smaller and faster code at -O0 (fast isel improvements)
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<li>The X86 backend, assembler and disassembler now have full support for AVX 1.
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To enable it pass <code>-mavx</code> to the compiler. AVX2 implementation is
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underway on mainline.</li>
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<li>The integrated assembler and disassembler now support a broad range of new
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instructions including Atom, Ivy Bridge, <a
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href="http://en.wikipedia.org/wiki/SSE4a">SSE4a/BMI</a> instructions, <a
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href="http://en.wikipedia.org/wiki/RdRand">rdrand</a> and many others.</li>
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<li>The X86 backend now fully supports the <a href="http://llvm.org/PR879">X87
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floating point stack inline assembly constraints</a>.</li>
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<li>The integrated assembler now supports the <tt>.code32</tt> and
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<tt>.code64</tt> directives to switch between 32-bit and 64-bit
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instructions.</li>
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<li>The X86 backend now synthesizes horizontal add/sub instructions from generic
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vector code when the appropriate instructions are enabled.</li>
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<li>The X86-64 backend generates smaller and faster code at -O0 due to
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improvements in fast instruction selection.</li>
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<li><a href="http://code.google.com/p/nativeclient/">Native Client</a>
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subtarget support has been added.</li>
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<li>The CRC32 intrinsics have been renamed. The intrinsics were previously
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<code>@llvm.x86.sse42.crc32.[8|16|32]</code>
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and <code>@llvm.x86.sse42.crc64.[8|64]</code>. They have been renamed to
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<code>@llvm.x86.sse42.crc32.32.[8|16|32]</code> and
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<code>@llvm.x86.sse42.crc32.64.[8|64]</code>.</li>
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</ul>
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</div>
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