From 2f21452ba1ee5bde8fee438b4cf1a1ce95beb6ca Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 24 Oct 2013 08:28:24 +0000 Subject: [PATCH] [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. When generating the IfTrue basic block during the F128CSEL pseudo-instruction handling, the NZCV live-in for the newly created BB wasn't being added. This caused a fault during MI-sched/live range calculation when the predecessor for the fall-through BB didn't have a live-in for phys-reg as expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelLowering.cpp | 8 ++++++-- test/CodeGen/AArch64/regress-fp128-livein.ll | 17 +++++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/AArch64/regress-fp128-livein.ll diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 40ed8af5517..c6b1d7a5412 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -699,6 +699,12 @@ AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI, MBB->addSuccessor(TrueBB); MBB->addSuccessor(EndBB); + if (!NZCVKilled) { + // NZCV is live-through TrueBB. + TrueBB->addLiveIn(AArch64::NZCV); + EndBB->addLiveIn(AArch64::NZCV); + } + // IfTrue: // str qIFTRUE, [sp] BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR)) @@ -713,8 +719,6 @@ AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI, // Done: // ldr qDEST, [sp] // [... rest of incoming MBB ...] - if (!NZCVKilled) - EndBB->addLiveIn(AArch64::NZCV); MachineInstr *StartOfEnd = EndBB->begin(); BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg) .addFrameIndex(ScratchFI) diff --git a/test/CodeGen/AArch64/regress-fp128-livein.ll b/test/CodeGen/AArch64/regress-fp128-livein.ll new file mode 100644 index 00000000000..cb8432a7e4e --- /dev/null +++ b/test/CodeGen/AArch64/regress-fp128-livein.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s + +; Regression test for NZCV reg live-in not being added to fp128csel IfTrue BB, +; causing a crash during live range calc. +define void @fp128_livein(i64 %a) { + %tobool = icmp ne i64 %a, 0 + %conv = zext i1 %tobool to i32 + %conv2 = sitofp i32 %conv to fp128 + %conv6 = sitofp i32 %conv to double + %call3 = tail call i32 @g(fp128 %conv2) + %call8 = tail call i32 @h(double %conv6) + ret void +} + +declare i32 @f() +declare i32 @g(fp128) +declare i32 @h(double)