mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
ARM: implement ldrex, strex and clrex intrinsics
Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186392 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
103ba845f0
commit
2f438131f1
@ -34,12 +34,15 @@ def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Load and Store exclusive doubleword
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// Load, Store and Clear exclusive
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def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
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def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
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def int_arm_clrex : Intrinsic<[]>;
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def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
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llvm_ptr_ty], [IntrReadWriteArgMem]>;
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def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty],
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[IntrReadArgMem]>;
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llvm_ptr_ty]>;
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def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
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//===----------------------------------------------------------------------===//
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// VFP
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@ -175,6 +175,7 @@ public:
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SDValue &OffImm);
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bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
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SDValue &OffReg, SDValue &ShImm);
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bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
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inline bool is_so_imm(unsigned Imm) const {
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return ARM_AM::getSOImmVal(Imm) != -1;
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@ -1417,6 +1418,34 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
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return true;
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}
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bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
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SDValue &OffImm) {
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// This *must* succeed since it's used for the irreplacable ldrex and strex
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// instructions.
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Base = N;
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OffImm = CurDAG->getTargetConstant(0, MVT::i32);
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if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
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return true;
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ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
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if (!RHS)
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return true;
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uint32_t RHSC = (int)RHS->getZExtValue();
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if (RHSC > 1020 || RHSC % 4 != 0)
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return true;
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy());
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}
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OffImm = CurDAG->getTargetConstant(RHSC / 4, MVT::i32);
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return true;
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}
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//===--------------------------------------------------------------------===//
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/// getAL - Returns a ARMCC::AL immediate node.
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@ -10838,6 +10838,30 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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Info.writeMem = true;
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return true;
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}
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case Intrinsic::arm_ldrex: {
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PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
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Info.opc = ISD::INTRINSIC_W_CHAIN;
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Info.memVT = MVT::getVT(PtrTy->getElementType());
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Info.ptrVal = I.getArgOperand(0);
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Info.offset = 0;
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Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
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Info.vol = true;
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Info.readMem = true;
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Info.writeMem = false;
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return true;
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}
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case Intrinsic::arm_strex: {
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PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
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Info.opc = ISD::INTRINSIC_W_CHAIN;
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Info.memVT = MVT::getVT(PtrTy->getElementType());
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Info.ptrVal = I.getArgOperand(1);
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Info.offset = 0;
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Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
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Info.vol = true;
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Info.readMem = false;
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Info.writeMem = true;
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return true;
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}
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case Intrinsic::arm_strexd: {
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Info.opc = ISD::INTRINSIC_W_CHAIN;
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Info.memVT = MVT::i64;
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@ -4383,14 +4383,44 @@ let usesCustomInserter = 1 in {
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[(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
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}
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def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def strex_1 : PatFrag<(ops node:$val, node:$ptr),
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(int_arm_strex node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def strex_2 : PatFrag<(ops node:$val, node:$ptr),
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(int_arm_strex node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def strex_4 : PatFrag<(ops node:$val, node:$ptr),
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(int_arm_strex node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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let mayLoad = 1 in {
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def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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NoItinerary,
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"ldrexb", "\t$Rt, $addr", []>;
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"ldrexb", "\t$Rt, $addr",
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[(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
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def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
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NoItinerary, "ldrexh", "\t$Rt, $addr",
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[(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
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def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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NoItinerary, "ldrex", "\t$Rt, $addr", []>;
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NoItinerary, "ldrex", "\t$Rt, $addr",
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[(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
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let hasExtraDefRegAllocReq = 1 in
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def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
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NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
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@ -4400,11 +4430,14 @@ def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
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let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
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def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
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NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
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NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
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[(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>;
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def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
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NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
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NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
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[(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>;
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def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
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NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
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NoItinerary, "strex", "\t$Rd, $Rt, $addr",
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[(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>;
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let hasExtraSrcRegAllocReq = 1 in
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def STREXD : AIstrex<0b01, (outs GPR:$Rd),
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(ins GPRPairOp:$Rt, addr_offset_none:$addr),
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@ -4414,11 +4447,21 @@ def STREXD : AIstrex<0b01, (outs GPR:$Rd),
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}
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def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
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def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
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[(int_arm_clrex)]>,
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Requires<[IsARM, HasV7]> {
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let Inst{31-0} = 0b11110101011111111111000000011111;
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}
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def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
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(LDREXB addr_offset_none:$addr)>;
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def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
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(LDREXH addr_offset_none:$addr)>;
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def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
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(STREXB GPR:$Rt, addr_offset_none:$addr)>;
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def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
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(STREXH GPR:$Rt, addr_offset_none:$addr)>;
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// SWP/SWPB are deprecated in V6/V7.
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let mayLoad = 1, mayStore = 1 in {
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def SWP : AIswp<0, (outs GPRnopc:$Rt),
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@ -251,7 +251,8 @@ def t2am_imm8s4_offset : Operand<i32> {
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def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
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let Name = "MemImm0_1020s4Offset";
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}
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def t2addrmode_imm0_1020s4 : Operand<i32> {
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def t2addrmode_imm0_1020s4 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
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let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
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let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
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let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
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@ -3201,13 +3202,16 @@ class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
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let mayLoad = 1 in {
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def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
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AddrModeNone, 4, NoItinerary,
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"ldrexb", "\t$Rt, $addr", "", []>;
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"ldrexb", "\t$Rt, $addr", "",
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[(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
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def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
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AddrModeNone, 4, NoItinerary,
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"ldrexh", "\t$Rt, $addr", "", []>;
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"ldrexh", "\t$Rt, $addr", "",
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[(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
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def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
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AddrModeNone, 4, NoItinerary,
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"ldrex", "\t$Rt, $addr", "", []> {
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"ldrex", "\t$Rt, $addr", "",
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[(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]> {
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bits<4> Rt;
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bits<12> addr;
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let Inst{31-27} = 0b11101;
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@ -3232,16 +3236,22 @@ let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
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def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
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(ins rGPR:$Rt, addr_offset_none:$addr),
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AddrModeNone, 4, NoItinerary,
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"strexb", "\t$Rd, $Rt, $addr", "", []>;
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"strexb", "\t$Rd, $Rt, $addr", "",
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[(set rGPR:$Rd, (strex_1 rGPR:$Rt,
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addr_offset_none:$addr))]>;
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def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
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(ins rGPR:$Rt, addr_offset_none:$addr),
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AddrModeNone, 4, NoItinerary,
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"strexh", "\t$Rd, $Rt, $addr", "", []>;
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"strexh", "\t$Rd, $Rt, $addr", "",
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[(set rGPR:$Rd, (strex_2 rGPR:$Rt,
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addr_offset_none:$addr))]>;
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def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
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t2addrmode_imm0_1020s4:$addr),
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AddrModeNone, 4, NoItinerary,
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"strex", "\t$Rd, $Rt, $addr", "",
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[]> {
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[(set rGPR:$Rd, (strex_4 rGPR:$Rt,
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t2addrmode_imm0_1020s4:$addr))]> {
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bits<4> Rd;
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bits<4> Rt;
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bits<12> addr;
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@ -3263,7 +3273,7 @@ def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
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}
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}
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def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
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def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
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Requires<[IsThumb2, HasV7]> {
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let Inst{31-16} = 0xf3bf;
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let Inst{15-14} = 0b10;
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@ -3274,6 +3284,15 @@ def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
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let Inst{3-0} = 0b1111;
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}
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def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
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(t2LDREXB addr_offset_none:$addr)>;
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def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
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(t2LDREXH addr_offset_none:$addr)>;
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def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
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(t2STREXB GPR:$Rt, addr_offset_none:$addr)>;
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def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
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(t2STREXH GPR:$Rt, addr_offset_none:$addr)>;
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//===----------------------------------------------------------------------===//
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// SJLJ Exception handling intrinsics
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// eh_sjlj_setjmp() is an instruction sequence to store the return
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@ -37,7 +37,7 @@ bool NVPTXAllocaHoisting::runOnFunction(Function &function) {
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}
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char NVPTXAllocaHoisting::ID = 1;
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RegisterPass<NVPTXAllocaHoisting>
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static RegisterPass<NVPTXAllocaHoisting>
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X("alloca-hoisting", "Hoisting alloca instructions in non-entry "
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"blocks to the entry block");
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139
test/CodeGen/ARM/ldstrex.ll
Normal file
139
test/CodeGen/ARM/ldstrex.ll
Normal file
@ -0,0 +1,139 @@
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; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin > %t
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; RUN: FileCheck %s < %t
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; RUN: FileCheck %s < %t --check-prefix=CHECK-T2ADDRMODE
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%0 = type { i32, i32 }
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; CHECK: f0:
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; CHECK: ldrexd
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define i64 @f0(i8* %p) nounwind readonly {
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entry:
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%ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
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%0 = extractvalue %0 %ldrexd, 1
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%1 = extractvalue %0 %ldrexd, 0
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%2 = zext i32 %0 to i64
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%3 = zext i32 %1 to i64
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%shl = shl nuw i64 %2, 32
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%4 = or i64 %shl, %3
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ret i64 %4
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}
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; CHECK: f1:
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; CHECK: strexd
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define i32 @f1(i8* %ptr, i64 %val) nounwind {
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entry:
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%tmp4 = trunc i64 %val to i32
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%tmp6 = lshr i64 %val, 32
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%tmp7 = trunc i64 %tmp6 to i32
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%strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
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ret i32 %strexd
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}
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declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
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declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
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; CHECK: test_load_i8:
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; CHECK: ldrexb r0, [r0]
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; CHECK-NOT: uxtb
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define i32 @test_load_i8(i8* %addr) {
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%val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr)
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ret i32 %val
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}
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; CHECK: test_load_i16:
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; CHECK: ldrexh r0, [r0]
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; CHECK-NOT: uxth
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define i32 @test_load_i16(i16* %addr) {
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%val = call i32 @llvm.arm.ldrex.p0i16(i16* %addr)
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ret i32 %val
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}
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; CHECK: test_load_i32:
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; CHECK: ldrex r0, [r0]
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define i32 @test_load_i32(i32* %addr) {
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%val = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
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ret i32 %val
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}
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declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly
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declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly
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declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly
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; CHECK: test_store_i8:
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; CHECK-NOT: uxtb
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; CHECK: strexb r0, r1, [r2]
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define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
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%extval = zext i8 %val to i32
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%res = call i32 @llvm.arm.strex.p0i8(i32 %extval, i8* %addr)
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ret i32 %res
|
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}
|
||||
|
||||
; CHECK: test_store_i16:
|
||||
; CHECK-NOT: uxth
|
||||
; CHECK: strexh r0, r1, [r2]
|
||||
define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
|
||||
%extval = zext i16 %val to i32
|
||||
%res = call i32 @llvm.arm.strex.p0i16(i32 %extval, i16* %addr)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
; CHECK: test_store_i32:
|
||||
; CHECK: strex r0, r1, [r2]
|
||||
define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
|
||||
%res = call i32 @llvm.arm.strex.p0i32(i32 %val, i32* %addr)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
declare i32 @llvm.arm.strex.p0i8(i32, i8*) nounwind
|
||||
declare i32 @llvm.arm.strex.p0i16(i32, i16*) nounwind
|
||||
declare i32 @llvm.arm.strex.p0i32(i32, i32*) nounwind
|
||||
|
||||
; CHECK: test_clear:
|
||||
; CHECK: clrex
|
||||
define void @test_clear() {
|
||||
call void @llvm.arm.clrex()
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.arm.clrex() nounwind
|
||||
|
||||
@base = global i32* null
|
||||
|
||||
define void @excl_addrmode() {
|
||||
; CHECK-T2ADDRMODE: excl_addrmode:
|
||||
%base1020 = load i32** @base
|
||||
%offset1020 = getelementptr i32* %base1020, i32 255
|
||||
call i32 @llvm.arm.ldrex.p0i32(i32* %offset1020)
|
||||
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1020)
|
||||
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
|
||||
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
|
||||
|
||||
%base1024 = load i32** @base
|
||||
%offset1024 = getelementptr i32* %base1024, i32 256
|
||||
call i32 @llvm.arm.ldrex.p0i32(i32* %offset1024)
|
||||
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1024)
|
||||
; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024
|
||||
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
|
||||
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
|
||||
|
||||
%base1 = load i32** @base
|
||||
%addr8 = bitcast i32* %base1 to i8*
|
||||
%offset1_8 = getelementptr i8* %addr8, i32 1
|
||||
%offset1 = bitcast i8* %offset1_8 to i32*
|
||||
call i32 @llvm.arm.ldrex.p0i32(i32* %offset1)
|
||||
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1)
|
||||
; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1
|
||||
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
|
||||
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
|
||||
|
||||
%local = alloca i8, i32 1024
|
||||
%local32 = bitcast i8* %local to i32*
|
||||
call i32 @llvm.arm.ldrex.p0i32(i32* %local32)
|
||||
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32)
|
||||
; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
|
||||
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
|
||||
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
|
||||
|
||||
ret void
|
||||
}
|
||||
@ -1,33 +0,0 @@
|
||||
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
|
||||
|
||||
%0 = type { i32, i32 }
|
||||
|
||||
; CHECK-LABEL: f0:
|
||||
; CHECK: ldrexd
|
||||
define i64 @f0(i8* %p) nounwind readonly {
|
||||
entry:
|
||||
%ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
|
||||
%0 = extractvalue %0 %ldrexd, 1
|
||||
%1 = extractvalue %0 %ldrexd, 0
|
||||
%2 = zext i32 %0 to i64
|
||||
%3 = zext i32 %1 to i64
|
||||
%shl = shl nuw i64 %2, 32
|
||||
%4 = or i64 %shl, %3
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: strexd
|
||||
define i32 @f1(i8* %ptr, i64 %val) nounwind {
|
||||
entry:
|
||||
%tmp4 = trunc i64 %val to i32
|
||||
%tmp6 = lshr i64 %val, 32
|
||||
%tmp7 = trunc i64 %tmp6 to i32
|
||||
%strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
|
||||
ret i32 %strexd
|
||||
}
|
||||
|
||||
declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
|
||||
declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
|
||||
|
||||
Loading…
Reference in New Issue
Block a user