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Add RA to the set of registers that are defined if instruction is a call.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-10-05 18:11:44 +00:00
parent 2dbb46a0a0
commit 2f52338f50
1 changed files with 4 additions and 4 deletions
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8
lib/Target/Mips/MipsDelaySlotFiller.cpp
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@ -218,13 +218,13 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
SmallSet<unsigned, 32>& RegDefs,
SmallSet<unsigned, 32>& RegUses) {
// If MI is a call or return, just examine the explicit non-variadic operands.
// NOTE: $ra is not added to RegDefs, since currently $ra is reserved and
// no instruction that can possibly be put in a delay slot can read or
// write it.
MCInstrDesc MCID = MI->getDesc();
unsigned e = MCID.isCall() || MCID.isReturn() ? MCID.getNumOperands() :
MI->getNumOperands();
// Add RA to RegDefs to prevent users of RA from going into delay slot.
if (MCID.isCall())
RegDefs.insert(Mips::RA);
for (unsigned i = 0; i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);