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Add a -disable-16bit flag and associated support for experimenting with

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disabling the use of 16-bit operations on x86. This doesn't yet work for
inline asms with 16-bit constraints, vectors with 16-bit elements,
trampoline code, and perhaps other obscurities, but it's enough to try
some experiments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80930 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-09-03 17:18:51 +00:00
parent 7b4608dfa0
commit 2f67df794a
3 changed files with 55 additions and 9 deletions
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38
lib/Target/X86/X86ISelLowering.cpp
View File

@ -47,6 +47,14 @@ using namespace llvm;
static cl::opt<bool>
DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
// Disable16Bit - 16-bit operations typically have a larger encoding than
// corresponding 32-bit instructions, and 16-bit code is slow on some
// processors. This is an experimental flag to disable 16-bit operations
// (which forces them to be Legalized to 32-bit operations).
static cl::opt<bool>
Disable16Bit("disable-16bit", cl::Hidden,
cl::desc("Disable use of 16-bit instructions"));
// Forward declarations.
static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
SDValue V2);
@ -99,7 +107,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// Set up the register classes.
addRegisterClass(MVT::i8, X86::GR8RegisterClass);
addRegisterClass(MVT::i16, X86::GR16RegisterClass);
if (!Disable16Bit)
addRegisterClass(MVT::i16, X86::GR16RegisterClass);
addRegisterClass(MVT::i32, X86::GR32RegisterClass);
if (Subtarget->is64Bit())
addRegisterClass(MVT::i64, X86::GR64RegisterClass);
@ -108,9 +117,11 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// We don't accept any truncstore of integer registers.
setTruncStoreAction(MVT::i64, MVT::i32, Expand);
setTruncStoreAction(MVT::i64, MVT::i16, Expand);
if (!Disable16Bit)
setTruncStoreAction(MVT::i64, MVT::i16, Expand);
setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
setTruncStoreAction(MVT::i32, MVT::i16, Expand);
if (!Disable16Bit)
setTruncStoreAction(MVT::i32, MVT::i16, Expand);
setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
setTruncStoreAction(MVT::i16, MVT::i8, Expand);
@ -261,8 +272,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
if (Disable16Bit) {
setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
} else {
setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
}
setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
@ -279,13 +295,19 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::SELECT , MVT::i1 , Promote);
// X86 wants to expand cmov itself.
setOperationAction(ISD::SELECT , MVT::i8 , Custom);
setOperationAction(ISD::SELECT , MVT::i16 , Custom);
if (Disable16Bit)
setOperationAction(ISD::SELECT , MVT::i16 , Expand);
else
setOperationAction(ISD::SELECT , MVT::i16 , Custom);
setOperationAction(ISD::SELECT , MVT::i32 , Custom);
setOperationAction(ISD::SELECT , MVT::f32 , Custom);
setOperationAction(ISD::SELECT , MVT::f64 , Custom);
setOperationAction(ISD::SELECT , MVT::f80 , Custom);
setOperationAction(ISD::SETCC , MVT::i8 , Custom);
setOperationAction(ISD::SETCC , MVT::i16 , Custom);
if (Disable16Bit)
setOperationAction(ISD::SETCC , MVT::i16 , Expand);
else
setOperationAction(ISD::SETCC , MVT::i16 , Custom);
setOperationAction(ISD::SETCC , MVT::i32 , Custom);
setOperationAction(ISD::SETCC , MVT::f32 , Custom);
setOperationAction(ISD::SETCC , MVT::f64 , Custom);
@ -1085,7 +1107,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
SmallVector<SDValue, 6> RetOps;
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {

12
lib/Target/X86/X86Instr64bit.td
View File

@ -2050,3 +2050,15 @@ let isTwoAddress = 1 in {
}
defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
// -disable-16bit support.
def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
(MOV16mi addr:$dst, imm:$src)>;
def : Pat<(truncstorei16 GR64:$src, addr:$dst),
(MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
def : Pat<(i64 (sextloadi16 addr:$dst)),
(MOVSX64rm16 addr:$dst)>;
def : Pat<(i64 (zextloadi16 addr:$dst)),
(MOVZX64rm16 addr:$dst)>;
def : Pat<(i64 (extloadi16 addr:$dst)),
(MOVZX64rm16 addr:$dst)>;

14
lib/Target/X86/X86InstrInfo.td
View File

@ -565,7 +565,7 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
[(X86retflag 0)]>;
def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"ret\t$amt",
[(X86retflag imm:$amt)]>;
[(X86retflag timm:$amt)]>;
}
// All branches are RawFrm, Void, Branch, and Terminators
@ -4168,6 +4168,18 @@ def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
(implicit EFLAGS)),
(DEC32m addr:$dst)>, Requires<[In32BitMode]>;
// -disable-16bit support.
def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
(MOV16mi addr:$dst, imm:$src)>;
def : Pat<(truncstorei16 GR32:$src, addr:$dst),
(MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
def : Pat<(i32 (sextloadi16 addr:$dst)),
(MOVSX32rm16 addr:$dst)>;
def : Pat<(i32 (zextloadi16 addr:$dst)),
(MOVZX32rm16 addr:$dst)>;
def : Pat<(i32 (extloadi16 addr:$dst)),
(MOVZX32rm16 addr:$dst)>;
//===----------------------------------------------------------------------===//
// Floating Point Stack Support
//===----------------------------------------------------------------------===//