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Add support for the convergent flag at the MC and MachineInstr levels.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238450 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2015-05-28 18:33:39 +00:00
parent 4c9279423e
commit 2f6ca834ff
6 changed files with 51 additions and 32 deletions
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utils/TableGen/CodeGenInstruction.cpp
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@@ -320,6 +320,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isRegSequence = R->getValueAsBit("isRegSequence");
isExtractSubreg = R->getValueAsBit("isExtractSubreg");
isInsertSubreg = R->getValueAsBit("isInsertSubreg");
isConvergent = R->getValueAsBit("isConvergent");
bool Unset;
mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset);