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Some more SSE 4.1 intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46696 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2539,6 +2539,7 @@ let isTwoAddress = 1 in {
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}
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}
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// FIXME: are these really two-address?
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defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
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int_x86_ssse3_pabs_b,
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int_x86_ssse3_pabs_b_128>;
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@ -3045,14 +3046,14 @@ def : Pat<(store (v16i8 VR128:$src), addr:$dst),
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// SSE4.1 Instruction Templates:
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//
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// SS418I - SSE 4.1 instructions with T8 prefix.
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// SS48I - SSE 4.1 instructions with T8 prefix.
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// SS41AI - SSE 4.1 instructions with TA prefix.
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//
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class SS418I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE41]>;
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class SS41AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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class SS4AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
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@ -3062,74 +3063,136 @@ multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
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Intrinsic F32Int,
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Intrinsic V4F32Int,
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Intrinsic F64Int,
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Intrinsic V2F64Int,
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bit Commutable = 0> {
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Intrinsic V2F64Int> {
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// Intrinsic operation, reg.
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def SSr_Int : SS41AI<opcss, MRMSrcReg,
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def SSr_Int : SS4AI<opcss, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i32imm:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]> {
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let isCommutable = Commutable;
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}
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[(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
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OpSize;
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// Intrinsic operation, mem.
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def SSm_Int : SS41AI<opcss, MRMSrcMem,
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def SSm_Int : SS4AI<opcss, MRMSrcMem,
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(outs VR128:$dst), (ins ssmem:$src1, i32imm:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>;
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[(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
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OpSize;
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// Vector intrinsic operation, reg
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def PSr_Int : SS41AI<opcps, MRMSrcReg,
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def PSr_Int : SS4AI<opcps, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i32imm:$src2),
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!strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]> {
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let isCommutable = Commutable;
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}
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[(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
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OpSize;
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// Vector intrinsic operation, mem
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def PSm_Int : SS41AI<opcps, MRMSrcMem,
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def PSm_Int : SS4AI<opcps, MRMSrcMem,
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(outs VR128:$dst), (ins f128mem:$src1, i32imm:$src2),
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!strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (V4F32Int (load addr:$src1), imm:$src2))]>;
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[(set VR128:$dst, (V4F32Int (load addr:$src1),imm:$src2))]>,
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OpSize;
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// Intrinsic operation, reg.
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def SDr_Int : SS41AI<opcsd, MRMSrcReg,
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def SDr_Int : SS4AI<opcsd, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i32imm:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]> {
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let isCommutable = Commutable;
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}
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[(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
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OpSize;
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// Intrinsic operation, mem.
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def SDm_Int : SS41AI<opcsd, MRMSrcMem,
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def SDm_Int : SS4AI<opcsd, MRMSrcMem,
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(outs VR128:$dst), (ins sdmem:$src1, i32imm:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>;
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[(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
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OpSize;
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// Vector intrinsic operation, reg
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def PDr_Int : SS41AI<opcpd, MRMSrcReg,
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def PDr_Int : SS4AI<opcpd, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i32imm:$src2),
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!strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]> {
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let isCommutable = Commutable;
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}
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[(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
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OpSize;
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// Vector intrinsic operation, mem
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def PDm_Int : SS41AI<opcpd, MRMSrcMem,
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def PDm_Int : SS4AI<opcpd, MRMSrcMem,
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(outs VR128:$dst), (ins f128mem:$src1, i32imm:$src2),
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!strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (V2F64Int (load addr:$src1), imm:$src2))]>;
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[(set VR128:$dst, (V2F64Int (load addr:$src1),imm:$src2))]>,
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OpSize;
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}
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// FP round - roundss, roundps, roundsd, roundpd
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defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
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int_x86_sse41_round_ss, int_x86_sse41_round_ps,
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int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
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// SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
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multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
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Intrinsic IntId128> {
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def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
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def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
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}
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defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
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int_x86_sse41_phminposuw>;
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/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
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let isTwoAddress = 1 in {
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multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
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Intrinsic IntId128, bit Commutable = 0> {
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def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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}
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defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
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int_x86_sse41_pcmpeqq, 1>;
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defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
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int_x86_sse41_packusdw, 0>;
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defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
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int_x86_sse41_pminsb, 1>;
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defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
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int_x86_sse41_pminsd, 1>;
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defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
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int_x86_sse41_pminud, 1>;
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defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
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int_x86_sse41_pminuw, 1>;
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defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
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int_x86_sse41_pmaxsb, 1>;
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defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
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int_x86_sse41_pmaxsd, 1>;
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defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
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int_x86_sse41_pmaxud, 1>;
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defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
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int_x86_sse41_pmaxuw, 1>;
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defm PMULLD : SS41I_binop_rm_int<0x40, "pmulld",
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int_x86_sse41_pmulld, 1>;
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defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq",
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int_x86_sse41_pmuldq, 1>;
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