mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
[ARM] Remove target-specific ITOFP/FPTOI nodes
Anton tried this 5 years ago but it was reverted due to extra VMOVs being emitted. This can be easily fixed with a liberal application of patterns - matching loads/stores and extractelts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232958 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy
parent
fd58f22744
commit
2f729838f1
@ -614,6 +614,12 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FRINT, MVT::f64, Expand);
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setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
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setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
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setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
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setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
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}
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@ -869,14 +875,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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// Various VFP goodness
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if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
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// int <-> fp are custom expanded into bit_convert + ARMISD ops.
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if (Subtarget->hasVFP2()) {
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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}
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// FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
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if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
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setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
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@ -1033,11 +1031,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::RBIT: return "ARMISD::RBIT";
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case ARMISD::FTOSI: return "ARMISD::FTOSI";
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case ARMISD::FTOUI: return "ARMISD::FTOUI";
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case ARMISD::SITOF: return "ARMISD::SITOF";
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case ARMISD::UITOF: return "ARMISD::UITOF";
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case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
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case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
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case ARMISD::RRX: return "ARMISD::RRX";
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@ -3795,7 +3788,6 @@ SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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if (VT.isVector())
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return LowerVectorFP_TO_INT(Op, DAG);
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if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
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RTLIB::Libcall LC;
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if (Op.getOpcode() == ISD::FP_TO_SINT)
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@ -3808,20 +3800,7 @@ SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
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/*isSigned*/ false, SDLoc(Op)).first;
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}
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SDLoc dl(Op);
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unsigned Opc;
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Invalid opcode!");
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case ISD::FP_TO_SINT:
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Opc = ARMISD::FTOSI;
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break;
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case ISD::FP_TO_UINT:
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Opc = ARMISD::FTOUI;
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break;
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}
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Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
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return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
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return Op;
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}
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static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
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@ -3861,7 +3840,6 @@ SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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if (VT.isVector())
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return LowerVectorINT_TO_FP(Op, DAG);
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if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
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RTLIB::Libcall LC;
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if (Op.getOpcode() == ISD::SINT_TO_FP)
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@ -3874,21 +3852,7 @@ SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
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/*isSigned*/ false, SDLoc(Op)).first;
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}
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SDLoc dl(Op);
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unsigned Opc;
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Invalid opcode!");
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case ISD::SINT_TO_FP:
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Opc = ARMISD::SITOF;
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break;
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case ISD::UINT_TO_FP:
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Opc = ARMISD::UITOF;
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break;
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}
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Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
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return DAG.getNode(Opc, dl, VT, Op);
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return Op;
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}
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SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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@ -65,11 +65,6 @@ namespace llvm {
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RBIT, // ARM bitreverse instruction
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FTOSI, // FP to sint within a FP register.
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FTOUI, // FP to uint within a FP register.
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SITOF, // sint to FP within a FP register.
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UITOF, // uint to FP within a FP register.
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SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
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SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
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RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
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@ -983,7 +983,12 @@ class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> {
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class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM, HasV6];
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}
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class VFPPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [HasVFP2];
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}
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class VFPNoNEONPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
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}
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//===----------------------------------------------------------------------===//
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// Thumb Instruction Format Definitions.
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//
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@ -6158,6 +6158,21 @@ class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
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(v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
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SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
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class NVCVTIFPat<SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode GPR:$a)),
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(f32 (EXTRACT_SUBREG
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(v2f32 (Inst
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(INSERT_SUBREG
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(v2f32 (IMPLICIT_DEF)),
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(i32 (COPY_TO_REGCLASS GPR:$a, SPR)), ssub_0))),
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ssub_0))>;
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class NVCVTFIPat<SDNode OpNode, NeonI Inst>
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: NEONFPPat<(i32 (OpNode SPR:$a)),
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(i32 (EXTRACT_SUBREG
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(v2f32 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$a, ssub_0))),
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ssub_0))>;
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def : N3VSPat<fadd, VADDfd>;
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def : N3VSPat<fsub, VSUBfd>;
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def : N3VSPat<fmul, VMULfd>;
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@ -6173,10 +6188,22 @@ def : N2VSPat<fabs, VABSfd>;
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def : N2VSPat<fneg, VNEGfd>;
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def : N3VSPat<NEONfmax, VMAXfd>;
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def : N3VSPat<NEONfmin, VMINfd>;
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def : N2VSPat<arm_ftosi, VCVTf2sd>;
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def : N2VSPat<arm_ftoui, VCVTf2ud>;
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def : N2VSPat<arm_sitof, VCVTs2fd>;
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def : N2VSPat<arm_uitof, VCVTu2fd>;
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def : NVCVTFIPat<fp_to_sint, VCVTf2sd>;
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def : NVCVTFIPat<fp_to_uint, VCVTf2ud>;
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def : NVCVTIFPat<sint_to_fp, VCVTs2fd>;
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def : NVCVTIFPat<uint_to_fp, VCVTu2fd>;
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// NEON doesn't have any f64 conversions, so provide patterns to make
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// sure the VFP conversions match when extracting from a vector.
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def : VFPPat<(f64 (sint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
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(VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
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def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
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(VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
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def : VFPPat<(f64 (uint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
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(VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
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def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
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(VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
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// Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
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def : Pat<(f32 (bitconvert GPR:$a)),
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@ -11,16 +11,10 @@
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//
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//===----------------------------------------------------------------------===//
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def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
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def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
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def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
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def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
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def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
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def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
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@ -641,7 +635,7 @@ multiclass vcvt_inst<string opc, bits<2> rm,
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def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
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[(set SPR:$Sd, (arm_ftosi (node SPR:$Sm)))]>,
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[]>,
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Requires<[HasFPARMv8]> {
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let Inst{17-16} = rm;
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}
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@ -649,7 +643,7 @@ multiclass vcvt_inst<string opc, bits<2> rm,
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def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
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[(set SPR:$Sd, (arm_ftoui (node SPR:$Sm)))]>,
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[]>,
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Requires<[HasFPARMv8]> {
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let Inst{17-16} = rm;
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}
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@ -657,7 +651,7 @@ multiclass vcvt_inst<string opc, bits<2> rm,
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def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
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(outs SPR:$Sd), (ins DPR:$Dm),
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NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
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[(set SPR:$Sd, (arm_ftosi (f64 (node (f64 DPR:$Dm)))))]>,
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[]>,
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Requires<[HasFPARMv8, HasDPVFP]> {
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bits<5> Dm;
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@ -672,7 +666,7 @@ multiclass vcvt_inst<string opc, bits<2> rm,
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def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
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(outs SPR:$Sd), (ins DPR:$Dm),
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NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
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[(set SPR:$Sd, (arm_ftoui (f64 (node (f64 DPR:$Dm)))))]>,
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[]>,
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Requires<[HasFPARMv8, HasDPVFP]> {
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bits<5> Dm;
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@ -684,6 +678,27 @@ multiclass vcvt_inst<string opc, bits<2> rm,
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let Inst{8} = 1;
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}
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}
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let Predicates = [HasFPARMv8] in {
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def : Pat<(i32 (fp_to_sint (node SPR:$a))),
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(COPY_TO_REGCLASS
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(!cast<Instruction>(NAME#"SS") SPR:$a),
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GPR)>;
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def : Pat<(i32 (fp_to_uint (node SPR:$a))),
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(COPY_TO_REGCLASS
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(!cast<Instruction>(NAME#"US") SPR:$a),
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GPR)>;
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}
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let Predicates = [HasFPARMv8, HasDPVFP] in {
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def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))),
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(COPY_TO_REGCLASS
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(!cast<Instruction>(NAME#"SD") DPR:$a),
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GPR)>;
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def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))),
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(COPY_TO_REGCLASS
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(!cast<Instruction>(NAME#"UD") DPR:$a),
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GPR)>;
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}
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}
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defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
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@ -988,14 +1003,22 @@ class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
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def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
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(outs DPR:$Dd), (ins SPR:$Sm),
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IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
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[(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
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[]> {
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let Inst{7} = 1; // s32
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}
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let Predicates=[HasVFP2, HasDPVFP] in {
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def : VFPPat<(f64 (sint_to_fp GPR:$a)),
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(VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
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def : VFPPat<(f64 (sint_to_fp (i32 (load addrmode5:$a)))),
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(VSITOD (VLDRS addrmode5:$a))>;
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}
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def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
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(outs SPR:$Sd),(ins SPR:$Sm),
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IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
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[(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
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[]> {
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let Inst{7} = 1; // s32
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// Some single precision VFP instructions may be executed on both NEON and
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@ -1003,17 +1026,31 @@ def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
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let D = VFPNeonA8Domain;
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}
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def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)),
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(VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
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def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (load addrmode5:$a)))),
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(VSITOS (VLDRS addrmode5:$a))>;
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def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
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(outs DPR:$Dd), (ins SPR:$Sm),
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IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
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[(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
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[]> {
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let Inst{7} = 0; // u32
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}
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let Predicates=[HasVFP2, HasDPVFP] in {
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def : VFPPat<(f64 (uint_to_fp GPR:$a)),
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(VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
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def : VFPPat<(f64 (uint_to_fp (i32 (load addrmode5:$a)))),
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(VUITOD (VLDRS addrmode5:$a))>;
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}
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def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
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[(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
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[]> {
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let Inst{7} = 0; // u32
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// Some single precision VFP instructions may be executed on both NEON and
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@ -1021,6 +1058,12 @@ def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
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let D = VFPNeonA8Domain;
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}
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def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)),
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(VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
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def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (load addrmode5:$a)))),
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(VUITOS (VLDRS addrmode5:$a))>;
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// FP -> Int:
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class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
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@ -1063,14 +1106,22 @@ class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
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def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
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(outs SPR:$Sd), (ins DPR:$Dm),
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IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
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[(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
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[]> {
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let Inst{7} = 1; // Z bit
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}
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let Predicates=[HasVFP2, HasDPVFP] in {
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def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
|
||||
(COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
|
||||
|
||||
def : VFPPat<(store (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
|
||||
(VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
|
||||
}
|
||||
|
||||
def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
|
||||
[]> {
|
||||
let Inst{7} = 1; // Z bit
|
||||
|
||||
// Some single precision VFP instructions may be executed on both NEON and
|
||||
@ -1078,17 +1129,31 @@ def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
|
||||
let D = VFPNeonA8Domain;
|
||||
}
|
||||
|
||||
def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
|
||||
(COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
|
||||
|
||||
def : VFPNoNEONPat<(store (i32 (fp_to_sint (f32 SPR:$a))), addrmode5:$ptr),
|
||||
(VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
|
||||
|
||||
def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
|
||||
(outs SPR:$Sd), (ins DPR:$Dm),
|
||||
IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
|
||||
[(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
|
||||
[]> {
|
||||
let Inst{7} = 1; // Z bit
|
||||
}
|
||||
|
||||
let Predicates=[HasVFP2, HasDPVFP] in {
|
||||
def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
|
||||
(COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
|
||||
|
||||
def : VFPPat<(store (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
|
||||
(VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
|
||||
}
|
||||
|
||||
def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
|
||||
[]> {
|
||||
let Inst{7} = 1; // Z bit
|
||||
|
||||
// Some single precision VFP instructions may be executed on both NEON and
|
||||
@ -1096,6 +1161,12 @@ def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
|
||||
let D = VFPNeonA8Domain;
|
||||
}
|
||||
|
||||
def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
|
||||
(COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
|
||||
|
||||
def : VFPNoNEONPat<(store (i32 (fp_to_uint (f32 SPR:$a))), addrmode5:$ptr),
|
||||
(VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
|
||||
|
||||
// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
|
||||
let Uses = [FPSCR] in {
|
||||
// FIXME: Verify encoding after integrated assembler is working.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user