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synced 2024-08-17 05:29:24 +00:00
Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
results in better code for globals. Also, unbreak the local CSE for GlobalValue stub loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56371 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -44,15 +44,10 @@ unsigned FastISel::getRegForValue(Value *V) {
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}
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if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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if (CI->getValue().getActiveBits() > 64)
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return TargetMaterializeConstant(CI);
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// Don't cache constant materializations. To do so would require
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// tracking what uses they dominate.
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if (CI->getValue().getActiveBits() <= 64)
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Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
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} else if (isa<GlobalValue>(V)) {
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return TargetMaterializeConstant(cast<Constant>(V));
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} else if (isa<AllocaInst>(V)) {
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return TargetMaterializeAlloca(cast<AllocaInst>(V));
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Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
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} else if (isa<ConstantPointerNull>(V)) {
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Reg = FastEmit_i(VT, VT, ISD::Constant, 0);
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} else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
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@ -64,18 +59,15 @@ unsigned FastISel::getRegForValue(Value *V) {
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uint64_t x[2];
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uint32_t IntBitWidth = IntVT.getSizeInBits();
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if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
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APFloat::rmTowardZero) != APFloat::opOK)
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return TargetMaterializeConstant(CF);
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if (!Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
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APFloat::rmTowardZero) != APFloat::opOK) {
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APInt IntVal(IntBitWidth, 2, x);
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unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
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ISD::Constant, IntVal.getZExtValue());
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if (IntegerReg == 0)
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return TargetMaterializeConstant(CF);
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if (IntegerReg != 0)
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Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
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if (Reg == 0)
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return TargetMaterializeConstant(CF);
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}
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}
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} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
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if (!SelectOperator(CE, CE->getOpcode())) return 0;
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@ -88,8 +80,10 @@ unsigned FastISel::getRegForValue(Value *V) {
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}
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if (!Reg && isa<Constant>(V))
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return TargetMaterializeConstant(cast<Constant>(V));
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Reg = TargetMaterializeConstant(cast<Constant>(V));
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// Don't cache constant materializations in the general ValueMap.
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// To do so would require tracking what uses they dominate.
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LocalValueMap[V] = Reg;
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return Reg;
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}
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@ -72,10 +72,7 @@ private:
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bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
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unsigned &ResultReg);
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bool X86SelectConstAddr(Value *V, unsigned &Op0,
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bool isCall = false, bool inReg = false);
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bool X86SelectAddress(Value *V, X86AddressMode &AM);
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bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
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bool X86SelectLoad(Instruction *I);
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@ -281,56 +278,9 @@ bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
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return false;
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}
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/// X86SelectConstAddr - Select and emit code to materialize constant address.
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///
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bool X86FastISel::X86SelectConstAddr(Value *V, unsigned &Op0,
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bool isCall, bool inReg) {
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// FIXME: Only GlobalAddress for now.
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GlobalValue *GV = dyn_cast<GlobalValue>(V);
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if (!GV)
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return false;
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if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
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// Issue load from stub if necessary.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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} else {
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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}
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Op0 = createResultReg(RC);
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X86AddressMode AM;
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AM.GV = GV;
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addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
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// Prevent loading GV stub multiple times in same MBB.
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LocalValueMap[V] = Op0;
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} else if (inReg) {
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::LEA32r;
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RC = X86::GR32RegisterClass;
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} else {
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Opc = X86::LEA64r;
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RC = X86::GR64RegisterClass;
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}
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Op0 = createResultReg(RC);
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X86AddressMode AM;
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AM.GV = GV;
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addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
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// Prevent materializing GV address multiple times in same MBB.
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LocalValueMap[V] = Op0;
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}
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return true;
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}
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/// X86SelectAddress - Attempt to fill in an address from the given value.
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///
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bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
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bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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User *U;
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unsigned Opcode = Instruction::UserOp1;
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if (Instruction *I = dyn_cast<Instruction>(V)) {
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@ -345,19 +295,20 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
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default: break;
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case Instruction::BitCast:
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// Look past bitcasts.
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return X86SelectAddress(U->getOperand(0), AM);
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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case Instruction::IntToPtr:
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// Look past no-op inttoptrs.
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return X86SelectAddress(U->getOperand(0), AM);
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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case Instruction::PtrToInt:
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// Look past no-op ptrtoints.
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return X86SelectAddress(U->getOperand(0), AM);
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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case Instruction::Alloca: {
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if (isCall) break;
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// Do static allocas.
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const AllocaInst *A = cast<AllocaInst>(V);
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DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
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@ -369,15 +320,17 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
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}
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case Instruction::Add: {
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if (isCall) break;
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// Adds of constants are common and easy enough.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
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AM.Disp += CI->getZExtValue();
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return X86SelectAddress(U->getOperand(0), AM);
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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}
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break;
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}
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case Instruction::GetElementPtr: {
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if (isCall) break;
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// Pattern-match simple GEPs.
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uint64_t Disp = AM.Disp;
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unsigned IndexReg = AM.IndexReg;
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@ -414,7 +367,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
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AM.IndexReg = IndexReg;
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AM.Scale = Scale;
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AM.Disp = Disp;
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return X86SelectAddress(U->getOperand(0), AM);
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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unsupported_gep:
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// Ok, the GEP indices weren't all covered.
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break;
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@ -422,19 +375,37 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
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}
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// Handle constant address.
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// FIXME: If load type is something we can't handle, this can result in
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// a dead stub load instruction.
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if (isa<Constant>(V) && X86SelectConstAddr(V, AM.Base.Reg)) {
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if (AM.Base.Reg == 0)
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AM.GV = cast<GlobalValue>(V);
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if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
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if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
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// Check to see if we've already materialized this
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// value in a register in this block.
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if (unsigned Reg = LocalValueMap[V])
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return Reg;
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// Issue load from stub if necessary.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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} else {
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AM.Base.Reg = getRegForValue(V);
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if (AM.Base.Reg == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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}
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AM.Base.Reg = createResultReg(RC);
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X86AddressMode LocalAM;
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LocalAM.GV = GV;
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addFullAddress(BuildMI(MBB, TII.get(Opc), AM.Base.Reg), LocalAM);
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// Prevent loading GV stub multiple times in same MBB.
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LocalValueMap[V] = AM.Base.Reg;
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} else {
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AM.GV = GV;
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}
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return true;
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}
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return true;
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// If all else fails, just materialize the value in a register.
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AM.Base.Reg = getRegForValue(V);
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return AM.Base.Reg != 0;
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}
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/// X86SelectStore - Select and emit code to implement store instructions.
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@ -448,7 +419,7 @@ bool X86FastISel::X86SelectStore(Instruction* I) {
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return false;
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X86AddressMode AM;
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if (!X86SelectAddress(I->getOperand(1), AM))
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if (!X86SelectAddress(I->getOperand(1), AM, false))
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return false;
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return X86FastEmitStore(VT, Val, AM);
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@ -462,7 +433,7 @@ bool X86FastISel::X86SelectLoad(Instruction *I) {
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return false;
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X86AddressMode AM;
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if (!X86SelectAddress(I->getOperand(0), AM))
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if (!X86SelectAddress(I->getOperand(0), AM, false))
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return false;
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unsigned ResultReg = 0;
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@ -849,13 +820,19 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
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// Materialize callee address in a register. FIXME: GV address can be
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// handled with a CALLpcrel32 instead.
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unsigned CalleeOp = 0;
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if (!isa<Constant>(Callee) || !X86SelectConstAddr(Callee, CalleeOp, true)) {
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CalleeOp = getRegForValue(Callee);
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if (CalleeOp == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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X86AddressMode CalleeAM;
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if (!X86SelectAddress(Callee, CalleeAM, true))
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return false;
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unsigned CalleeOp = 0;
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GlobalValue *GV = 0;
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if (CalleeAM.Base.Reg != 0) {
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assert(CalleeAM.GV == 0);
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CalleeOp = CalleeAM.Base.Reg;
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} else if (CalleeAM.GV != 0) {
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assert(CalleeAM.GV != 0);
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GV = CalleeAM.GV;
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} else
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return false;
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}
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// Allow calls which produce i1 results.
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bool AndToI1 = false;
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@ -976,7 +953,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
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: (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
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MachineInstrBuilder MIB = CalleeOp
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? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
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:BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(cast<GlobalValue>(Callee));
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: BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV);
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// Add implicit physical register uses to the call.
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while (!RegArgs.empty()) {
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MIB.addReg(RegArgs.back());
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@ -1132,10 +1109,18 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
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break;
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}
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unsigned ResultReg = createResultReg(RC);
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// Materialize addresses with LEA instructions.
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if (isa<GlobalValue>(C)) {
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if (X86SelectConstAddr(C, ResultReg, false, true))
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X86AddressMode AM;
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if (X86SelectAddress(C, AM, false)) {
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if (TLI.getPointerTy() == MVT::i32)
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Opc = X86::LEA32r;
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else
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Opc = X86::LEA64r;
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unsigned ResultReg = createResultReg(RC);
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addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
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return ResultReg;
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}
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return 0;
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}
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@ -1148,13 +1133,14 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
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}
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unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
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unsigned ResultReg = createResultReg(RC);
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addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset);
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return ResultReg;
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}
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unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
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X86AddressMode AM;
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if (!X86SelectAddress(C, AM))
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if (!X86SelectAddress(C, AM, false))
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return 0;
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unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
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TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
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@ -1,5 +1,5 @@
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; RUN: llvm-as < %s | llc -fast-isel -mtriple=i386-apple-darwin | \
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; RUN: grep mov | grep lazy_ptr | count 2
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; RUN: grep lazy_ptr, | count 2
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; RUN: llvm-as < %s | llc -fast-isel -march=x86 -relocation-model=static | \
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; RUN: grep lea
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