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R600/SI: Fix SMRD pattern for offsets > 32 bits

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We were dropping the high bits of 64-bit immediate offsets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208431 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-05-09 16:42:21 +00:00
parent 561bb44525
commit 300094fd84
3 changed files with 24 additions and 7 deletions
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9
lib/Target/R600/SIInstrInfo.td
View File

@ -11,11 +11,6 @@
// SI DAG Nodes
//===----------------------------------------------------------------------===//
// SMRD takes a 64bit memory address and can only add an 32bit offset
def SIadd64bit32bit : SDNode<"ISD::ADD",
SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i32>]>
>;
def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
[SDNPMayLoad, SDNPMemOperand]
@ -111,6 +106,10 @@ def IMM16bit : PatLeaf <(imm),
[{return isUInt<16>(N->getZExtValue());}]
>;
def IMM32bit : PatLeaf <(imm),
[{return isUInt<32>(N->getZExtValue());}]
>;
def mubuf_vaddr_offset : PatFrag<
(ops node:$ptr, node:$offset, node:$imm_offset),
(add (add node:$ptr, node:$offset), node:$imm_offset)

4
lib/Target/R600/SIInstructions.td
View File

@ -1640,8 +1640,8 @@ multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
// 2. Offset loaded in an 32bit SGPR
def : Pat <
(constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)),
(vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset)))
(constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
(vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
>;
// 3. No offset at all

18
test/CodeGen/R600/smrd.ll
View File

@ -34,6 +34,24 @@ entry:
ret void
}
; SMRD load with a 64-bit offset
; CHECK-LABEL: @smrd3
; CHECK-DAG: S_MOV_B32 s[[SHI:[0-9]+]], 4
; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0
; FIXME: We don't need to copy these values to VGPRs
; CHECK-DAG: V_MOV_B32_e32 v[[VHI:[0-9]+]], s[[SHI]]
; CHECK-DAG: V_MOV_B32_e32 v[[VLO:[0-9]+]], s[[SLO]]
; FIXME: We should be able to use S_LOAD_DWORD here
; BUFFER_LOAD_DWORD v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] + v[[[VLO]]:[[VHI]]] + 0x0
define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
entry:
%0 = getelementptr i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32
%1 = load i32 addrspace(2)* %0
store i32 %1, i32 addrspace(1)* %out
ret void
}
; SMRD load using the load.const intrinsic with an immediate offset
; CHECK-LABEL: @smrd_load_const0
; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04