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Implement SELECT_CC (f32/f64) for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32762 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -73,6 +73,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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@ -745,7 +747,7 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Cmp;
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SDOperand ARMCC;
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LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG);
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return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
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return DAG.getNode(ARMISD::SELECT, Op.getValueType(), TrueVal, FalseVal, ARMCC, Cmp);
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}
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static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
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@ -102,7 +102,7 @@ def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
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def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
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def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>;
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def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
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def SDTarmfmstat : SDTypeProfile<0, 0, []>;
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@ -209,6 +209,18 @@ let isTwoAddress = 1 in {
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"mov$cc $dst, $true",
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[(set IntRegs:$dst, (armselect addr_mode1:$true,
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IntRegs:$false, imm:$cc))]>;
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def fcpyscond : InstARM<(ops FPRegs:$dst, FPRegs:$false,
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FPRegs:$true, CCOp:$cc),
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"fcpys$cc $dst, $true",
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[(set FPRegs:$dst, (armselect FPRegs:$true,
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FPRegs:$false, imm:$cc))]>;
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def fcpydcond : InstARM<(ops DFPRegs:$dst, DFPRegs:$false,
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DFPRegs:$true, CCOp:$cc),
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"fcpyd$cc $dst, $true",
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[(set DFPRegs:$dst, (armselect DFPRegs:$true,
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DFPRegs:$false, imm:$cc))]>;
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}
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def MUL : IntBinOp<"mul", mul>;
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