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Add proper emission of load/store double to stack slots for mips1 targets!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89821 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2009-11-25 00:36:00 +00:00
parent 7dbc610309
commit 302525b234
1 changed files with 44 additions and 22 deletions
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66
lib/Target/Mips/MipsInstrInfo.cpp
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@ -200,22 +200,33 @@ void MipsInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI, unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
unsigned Opc;
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
if (RC == Mips::CPURegsRegisterClass) if (RC == Mips::CPURegsRegisterClass)
Opc = Mips::SW; BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::SWC1;
else {
assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::SDC1;
}
BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI); .addImm(0).addFrameIndex(FI);
else if (RC == Mips::FGR32RegisterClass)
BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
else if (RC == Mips::AFGR64RegisterClass) {
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
BuildMI(MBB, I, DL, get(Mips::SDC1))
.addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
} else {
const TargetRegisterInfo *TRI =
MBB.getParent()->getTarget().getRegisterInfo();
const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
BuildMI(MBB, I, DL, get(Mips::SWC1))
.addReg(SubSet[0], getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
BuildMI(MBB, I, DL, get(Mips::SWC1))
.addReg(SubSet[1], getKillRegState(isKill))
.addImm(4).addFrameIndex(FI);
}
} else
llvm_unreachable("Register class not handled!");
} }
void MipsInstrInfo:: void MipsInstrInfo::
@ -223,19 +234,27 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI, unsigned DestReg, int FI,
const TargetRegisterClass *RC) const const TargetRegisterClass *RC) const
{ {
unsigned Opc;
if (RC == Mips::CPURegsRegisterClass)
Opc = Mips::LW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::LWC1;
else {
assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::LDC1;
}
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
if (RC == Mips::CPURegsRegisterClass)
BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
else if (RC == Mips::FGR32RegisterClass)
BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
else if (RC == Mips::AFGR64RegisterClass) {
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
} else {
const TargetRegisterInfo *TRI =
MBB.getParent()->getTarget().getRegisterInfo();
const unsigned *SubSet = TRI->getSubRegisters(DestReg);
BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
.addImm(0).addFrameIndex(FI);
BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
.addImm(4).addFrameIndex(FI);
}
} else
llvm_unreachable("Register class not handled!");
} }
MachineInstr *MipsInstrInfo:: MachineInstr *MipsInstrInfo::
@ -278,11 +297,14 @@ foldMemoryOperandImpl(MachineFunction &MF,
const TargetRegisterClass const TargetRegisterClass
*RC = RI.getRegClass(MI->getOperand(0).getReg()); *RC = RI.getRegClass(MI->getOperand(0).getReg());
unsigned StoreOpc, LoadOpc; unsigned StoreOpc, LoadOpc;
bool IsMips1 = TM.getSubtarget<MipsSubtarget>().isMips1();
if (RC == Mips::FGR32RegisterClass) { if (RC == Mips::FGR32RegisterClass) {
LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1; LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
} else { } else {
assert(RC == Mips::AFGR64RegisterClass); assert(RC == Mips::AFGR64RegisterClass);
// Mips1 doesn't have ldc/sdc instructions.
if (IsMips1) break;
LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1; LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
} }