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Let me introduce you to the early stages of the llvm backend for the alpha processor

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19764 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
2005-01-22 23:41:55 +00:00
parent 68cd65ea68
commit 304d0f3076
15 changed files with 2305 additions and 0 deletions
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lib/Target/Alpha/AlphaTargetMachine.cpp Normal file
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//===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -------===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
#include "Alpha.h"
#include "AlphaTargetMachine.h"
#include "llvm/Module.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/CommandLine.h"
#include <iostream>
using namespace llvm;
namespace {
// Register the targets
RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)");
}
AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL)
: TargetMachine("alpha", IL, true),
FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) //TODO: check these
//JITInfo(*this)
{}
bool AlphaTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE)
{
assert(0 && "TODO");
return false;
}
/// addPassesToEmitAssembly - Add passes to the specified pass manager
/// to implement a static compiler for this target.
///
bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM,
std::ostream &Out) {
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
// FIXME: Implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
// FIXME: Implement the switch instruction in the instruction selector!
PM.add(createLowerSwitchPass());
PM.add(createLowerConstantExpressionsPass());
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
PM.add(createAlphaPatternInstructionSelector(*this));
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));
PM.add(createRegisterAllocator());
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));
PM.add(createPrologEpilogCodeInserter());
// Must run branch selection immediately preceding the asm printer
//PM.add(createAlphaBranchSelectionPass());
PM.add(createAlphaCodePrinterPass(Out, *this));
PM.add(createMachineCodeDeleter());
return false;
}
//void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
// // FIXME: Implement efficient support for garbage collection intrinsics.
// PM.add(createLowerGCPass());
// // FIXME: Implement the invoke/unwind instructions!
// PM.add(createLowerInvokePass());
// // FIXME: Implement the switch instruction in the instruction selector!
// PM.add(createLowerSwitchPass());
// PM.add(createLowerConstantExpressionsPass());
// // Make sure that no unreachable blocks are instruction selected.
// PM.add(createUnreachableBlockEliminationPass());
// PM.add(createPPC32ISelSimple(TM));
// PM.add(createRegisterAllocator());
// PM.add(createPrologEpilogCodeInserter());
// // Must run branch selection immediately preceding the asm printer
// PM.add(createPPCBranchSelectionPass());
// if (PrintMachineCode)
// PM.add(createMachineFunctionPrinterPass(&std::cerr));
//}