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Don't call Predicate_* from X86 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -171,6 +171,17 @@ namespace {
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virtual void PreprocessISelDAG();
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inline bool immSext8(SDNode *N) const {
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return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
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}
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// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// sign extended field.
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inline bool i64immSExt32(SDNode *N) const {
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uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
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return (int64_t)v == (int32_t)v;
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}
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// Include the pieces autogenerated from the target description.
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#include "X86GenDAGISel.inc"
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@ -1396,7 +1407,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
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Opc = X86::LOCK_DEC16m;
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else if (isSub) {
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if (isCN) {
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if (Predicate_immSext8(Val.getNode()))
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_SUB16mi8;
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else
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Opc = X86::LOCK_SUB16mi;
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@ -1404,7 +1415,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
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Opc = X86::LOCK_SUB16mr;
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} else {
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if (isCN) {
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if (Predicate_immSext8(Val.getNode()))
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_ADD16mi8;
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else
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Opc = X86::LOCK_ADD16mi;
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@ -1419,7 +1430,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
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Opc = X86::LOCK_DEC32m;
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else if (isSub) {
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if (isCN) {
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if (Predicate_immSext8(Val.getNode()))
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_SUB32mi8;
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else
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Opc = X86::LOCK_SUB32mi;
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@ -1427,7 +1438,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
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Opc = X86::LOCK_SUB32mr;
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} else {
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if (isCN) {
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if (Predicate_immSext8(Val.getNode()))
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_ADD32mi8;
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else
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Opc = X86::LOCK_ADD32mi;
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@ -1443,17 +1454,17 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
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else if (isSub) {
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Opc = X86::LOCK_SUB64mr;
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if (isCN) {
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if (Predicate_immSext8(Val.getNode()))
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_SUB64mi8;
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else if (Predicate_i64immSExt32(Val.getNode()))
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else if (i64immSExt32(Val.getNode()))
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Opc = X86::LOCK_SUB64mi32;
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}
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} else {
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Opc = X86::LOCK_ADD64mr;
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if (isCN) {
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if (Predicate_immSext8(Val.getNode()))
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_ADD64mi8;
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else if (Predicate_i64immSExt32(Val.getNode()))
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else if (i64immSExt32(Val.getNode()))
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Opc = X86::LOCK_ADD64mi32;
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}
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}
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@ -73,11 +73,7 @@ def GetLo32XForm : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue());
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}]>;
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def i64immSExt32 : PatLeaf<(i64 imm), [{
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// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// sign extended field.
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return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
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}]>;
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def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>;
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def i64immZExt32 : PatLeaf<(i64 imm), [{
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@ -414,9 +414,7 @@ def X86_COND_O : PatLeaf<(i8 13)>;
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def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
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def X86_COND_S : PatLeaf<(i8 15)>;
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def immSext8 : PatLeaf<(imm), [{
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return N->getSExtValue() == (int8_t)N->getSExtValue();
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}]>;
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def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
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def i16immSExt8 : PatLeaf<(i16 immSext8)>;
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def i32immSExt8 : PatLeaf<(i32 immSext8)>;
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