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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Fold comparisons into select instructions, making much better code and
using our broad selection of movcc instructions. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12560 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -743,19 +743,20 @@ void ISel::InsertFPRegKills() {
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}
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// canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
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// the conditional branch instruction which is the only user of the cc
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// instruction. This is the case if the conditional branch is the only user of
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// the setcc, and if the setcc is in the same basic block as the conditional
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// branch. We also don't handle long arguments below, so we reject them here as
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// well.
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// canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
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// it into the conditional branch or select instruction which is the only user
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// of the cc instruction. This is the case if the conditional branch is the
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// only user of the setcc, and if the setcc is in the same basic block as the
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// conditional branch. We also don't handle long arguments below, so we reject
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// them here as well.
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//
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static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
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static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
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if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
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if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
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SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
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const Type *Ty = SCI->getOperand(0)->getType();
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if (Ty != Type::LongTy && Ty != Type::ULongTy)
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if (SCI->hasOneUse()) {
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Instruction *User = cast<Instruction>(SCI->use_back());
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if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
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SCI->getParent() == User->getParent() &&
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getClassB(SCI->getOperand(0)->getType()) != cLong)
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return SCI;
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}
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return 0;
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@ -907,7 +908,8 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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/// register, then move it to wherever the result should be.
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
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if (canFoldSetCCIntoBranchOrSelect(&I))
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return; // Fold this into a branch or select.
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unsigned DestReg = getReg(I);
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MachineBasicBlock::iterator MII = BB->end();
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@ -963,28 +965,82 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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FalseVal = ConstantExpr::getCast(F, Type::ShortTy);
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}
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// Get the value being branched on, and use it to set the condition codes.
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unsigned CondReg = getReg(Cond, MBB, IP);
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BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
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unsigned Opcode;
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if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
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// We successfully folded the setcc into the select instruction.
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
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IP);
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const Type *CompTy = SCI->getOperand(0)->getType();
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bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> cmovNE cmovNE
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// setne -> cmovE cmovE
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// setlt -> cmovGE cmovAE
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// setge -> cmovL cmovB
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// setgt -> cmovLE cmovBE
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// setle -> cmovG cmovA
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// ----
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// cmovNS // Used by comparison with 0 optimization
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// cmovS
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switch (SelectClass) {
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default:
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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case cByte:
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case cShort: {
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static const unsigned OpcodeTab[2][8] = {
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{ X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVAE16rr, X86::CMOVB16rr,
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X86::CMOVBE16rr, X86::CMOVA16rr, 0, 0 },
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{ X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVGE16rr, X86::CMOVL16rr,
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X86::CMOVLE16rr, X86::CMOVG16rr, X86::CMOVNS16rr, X86::CMOVS16rr },
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};
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Opcode = OpcodeTab[isSigned][OpNum];
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break;
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}
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case cInt:
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case cLong: {
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static const unsigned OpcodeTab[2][8] = {
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{ X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVAE32rr, X86::CMOVB32rr,
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X86::CMOVBE32rr, X86::CMOVA32rr, 0, 0 },
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{ X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVGE32rr, X86::CMOVL32rr,
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X86::CMOVLE32rr, X86::CMOVG32rr, X86::CMOVNS32rr, X86::CMOVS32rr },
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};
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Opcode = OpcodeTab[isSigned][OpNum];
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break;
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}
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}
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} else {
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// Get the value being branched on, and use it to set the condition codes.
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unsigned CondReg = getReg(Cond, MBB, IP);
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BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
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switch (SelectClass) {
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default:
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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case cByte:
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case cShort:
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Opcode = X86::CMOVE16rr;
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break;
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case cInt:
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case cLong:
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Opcode = X86::CMOVE32rr;
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break;
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}
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}
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unsigned TrueReg = getReg(TrueVal, MBB, IP);
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unsigned FalseReg = getReg(FalseVal, MBB, IP);
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unsigned RealDestReg = DestReg;
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unsigned Opcode;
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switch (SelectClass) {
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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case cByte:
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case cShort:
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Opcode = X86::CMOVE16rr;
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break;
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case cInt:
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case cLong:
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Opcode = X86::CMOVE32rr;
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break;
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}
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// Annoyingly enough, X86 doesn't HAVE 8-bit conditional moves. Because of
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// this, we have to promote the incoming values to 16 bits, perform a 16-bit
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@ -1126,7 +1182,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
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}
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// See if we can fold the setcc into the branch itself...
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SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
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SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
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if (SCI == 0) {
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// Nope, cannot fold setcc into this branch. Emit a branch on a condition
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// computed some other way...
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@ -743,19 +743,20 @@ void ISel::InsertFPRegKills() {
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}
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// canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
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// the conditional branch instruction which is the only user of the cc
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// instruction. This is the case if the conditional branch is the only user of
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// the setcc, and if the setcc is in the same basic block as the conditional
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// branch. We also don't handle long arguments below, so we reject them here as
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// well.
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// canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
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// it into the conditional branch or select instruction which is the only user
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// of the cc instruction. This is the case if the conditional branch is the
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// only user of the setcc, and if the setcc is in the same basic block as the
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// conditional branch. We also don't handle long arguments below, so we reject
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// them here as well.
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//
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static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
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static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
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if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
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if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
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SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
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const Type *Ty = SCI->getOperand(0)->getType();
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if (Ty != Type::LongTy && Ty != Type::ULongTy)
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if (SCI->hasOneUse()) {
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Instruction *User = cast<Instruction>(SCI->use_back());
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if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
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SCI->getParent() == User->getParent() &&
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getClassB(SCI->getOperand(0)->getType()) != cLong)
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return SCI;
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}
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return 0;
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@ -907,7 +908,8 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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/// register, then move it to wherever the result should be.
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
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if (canFoldSetCCIntoBranchOrSelect(&I))
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return; // Fold this into a branch or select.
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unsigned DestReg = getReg(I);
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MachineBasicBlock::iterator MII = BB->end();
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@ -963,28 +965,82 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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FalseVal = ConstantExpr::getCast(F, Type::ShortTy);
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}
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// Get the value being branched on, and use it to set the condition codes.
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unsigned CondReg = getReg(Cond, MBB, IP);
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BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
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unsigned Opcode;
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if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
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// We successfully folded the setcc into the select instruction.
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
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IP);
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const Type *CompTy = SCI->getOperand(0)->getType();
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bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> cmovNE cmovNE
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// setne -> cmovE cmovE
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// setlt -> cmovGE cmovAE
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// setge -> cmovL cmovB
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// setgt -> cmovLE cmovBE
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// setle -> cmovG cmovA
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// ----
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// cmovNS // Used by comparison with 0 optimization
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// cmovS
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switch (SelectClass) {
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default:
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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case cByte:
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case cShort: {
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static const unsigned OpcodeTab[2][8] = {
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{ X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVAE16rr, X86::CMOVB16rr,
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X86::CMOVBE16rr, X86::CMOVA16rr, 0, 0 },
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{ X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVGE16rr, X86::CMOVL16rr,
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X86::CMOVLE16rr, X86::CMOVG16rr, X86::CMOVNS16rr, X86::CMOVS16rr },
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};
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Opcode = OpcodeTab[isSigned][OpNum];
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break;
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}
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case cInt:
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case cLong: {
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static const unsigned OpcodeTab[2][8] = {
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{ X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVAE32rr, X86::CMOVB32rr,
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X86::CMOVBE32rr, X86::CMOVA32rr, 0, 0 },
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{ X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVGE32rr, X86::CMOVL32rr,
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X86::CMOVLE32rr, X86::CMOVG32rr, X86::CMOVNS32rr, X86::CMOVS32rr },
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};
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Opcode = OpcodeTab[isSigned][OpNum];
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break;
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}
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}
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} else {
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// Get the value being branched on, and use it to set the condition codes.
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unsigned CondReg = getReg(Cond, MBB, IP);
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BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
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switch (SelectClass) {
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default:
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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case cByte:
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case cShort:
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Opcode = X86::CMOVE16rr;
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break;
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case cInt:
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case cLong:
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Opcode = X86::CMOVE32rr;
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break;
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}
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}
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unsigned TrueReg = getReg(TrueVal, MBB, IP);
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unsigned FalseReg = getReg(FalseVal, MBB, IP);
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unsigned RealDestReg = DestReg;
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unsigned Opcode;
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switch (SelectClass) {
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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case cByte:
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case cShort:
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Opcode = X86::CMOVE16rr;
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break;
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case cInt:
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case cLong:
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Opcode = X86::CMOVE32rr;
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break;
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}
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// Annoyingly enough, X86 doesn't HAVE 8-bit conditional moves. Because of
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// this, we have to promote the incoming values to 16 bits, perform a 16-bit
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@ -1126,7 +1182,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
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}
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// See if we can fold the setcc into the branch itself...
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SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
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SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
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if (SCI == 0) {
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// Nope, cannot fold setcc into this branch. Emit a branch on a condition
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// computed some other way...
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