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Add VSX Scalar loads and stores to the PPC back end
This patch corresponds to review: http://reviews.llvm.org/D9440 It adds a new register class to the PPC back end to contain single precision values in VSX registers. Additionally, it adds scalar loads and stores for VSX registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236755 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic
parent
9e31c0cf91
commit
308873bcb8
@ -132,6 +132,25 @@ static const MCPhysReg VSFRegs[64] = {
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PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
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PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
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};
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static const MCPhysReg VSSRegs[64] = {
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PPC::F0, PPC::F1, PPC::F2, PPC::F3,
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PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11,
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PPC::F12, PPC::F13, PPC::F14, PPC::F15,
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PPC::F16, PPC::F17, PPC::F18, PPC::F19,
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PPC::F20, PPC::F21, PPC::F22, PPC::F23,
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PPC::F24, PPC::F25, PPC::F26, PPC::F27,
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PPC::F28, PPC::F29, PPC::F30, PPC::F31,
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PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
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PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
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PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
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PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
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PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
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PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
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PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
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PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
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};
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static unsigned QFRegs[32] = {
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PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
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PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
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@ -577,6 +596,11 @@ public:
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Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
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}
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void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(VSSRegs[getVSReg()]));
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}
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void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
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@ -131,6 +131,26 @@ static const unsigned VSFRegs[] = {
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PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
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};
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static const unsigned VSSRegs[] = {
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PPC::F0, PPC::F1, PPC::F2, PPC::F3,
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PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11,
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PPC::F12, PPC::F13, PPC::F14, PPC::F15,
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PPC::F16, PPC::F17, PPC::F18, PPC::F19,
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PPC::F20, PPC::F21, PPC::F22, PPC::F23,
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PPC::F24, PPC::F25, PPC::F26, PPC::F27,
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PPC::F28, PPC::F29, PPC::F30, PPC::F31,
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PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
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PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
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PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
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PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
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PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
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PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
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PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
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PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
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};
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static const unsigned GPRegs[] = {
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PPC::R0, PPC::R1, PPC::R2, PPC::R3,
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PPC::R4, PPC::R5, PPC::R6, PPC::R7,
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@ -231,6 +251,12 @@ static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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return decodeRegisterClass(Inst, RegNo, VSFRegs);
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}
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static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSSRegs);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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@ -2734,7 +2734,10 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
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else if (N->getValueType(0) == MVT::i64)
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SelectCCOp = PPC::SELECT_CC_I8;
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else if (N->getValueType(0) == MVT::f32)
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SelectCCOp = PPC::SELECT_CC_F4;
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if (PPCSubTarget->hasP8Vector())
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SelectCCOp = PPC::SELECT_CC_VSSRC;
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else
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SelectCCOp = PPC::SELECT_CC_F4;
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else if (N->getValueType(0) == MVT::f64)
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if (PPCSubTarget->hasVSX())
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SelectCCOp = PPC::SELECT_CC_VSFRC;
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@ -3449,6 +3452,7 @@ void PPCDAGToDAGISel::PeepholeCROps() {
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case PPC::SELECT_QBRC:
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case PPC::SELECT_VRRC:
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case PPC::SELECT_VSFRC:
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case PPC::SELECT_VSSRC:
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case PPC::SELECT_VSRC: {
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SDValue Op = MachineNode->getOperand(0);
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if (Op.isMachineOpcode()) {
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@ -3759,6 +3763,7 @@ void PPCDAGToDAGISel::PeepholeCROps() {
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case PPC::SELECT_QBRC:
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case PPC::SELECT_VRRC:
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case PPC::SELECT_VSFRC:
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case PPC::SELECT_VSSRC:
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case PPC::SELECT_VSRC:
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if (Op1Set)
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ResNode = MachineNode->getOperand(1).getNode();
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@ -582,6 +582,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
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if (Subtarget.hasP8Vector())
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addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
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addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
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addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
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@ -2680,7 +2683,10 @@ PPCTargetLowering::LowerFormalArguments_32SVR4(
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RC = &PPC::GPRCRegClass;
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break;
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case MVT::f32:
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RC = &PPC::F4RCRegClass;
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if (Subtarget.hasP8Vector())
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RC = &PPC::VSSRCRegClass;
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else
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RC = &PPC::F4RCRegClass;
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break;
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case MVT::f64:
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if (Subtarget.hasVSX())
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@ -3094,7 +3100,10 @@ PPCTargetLowering::LowerFormalArguments_64SVR4(
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unsigned VReg;
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if (ObjectVT == MVT::f32)
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VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
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VReg = MF.addLiveIn(FPR[FPR_idx],
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Subtarget.hasP8Vector()
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? &PPC::VSSRCRegClass
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: &PPC::F4RCRegClass);
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else
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VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
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? &PPC::VSFRCRegClass
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@ -8383,6 +8392,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MI->getOpcode() == PPC::SELECT_CC_QBRC ||
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MI->getOpcode() == PPC::SELECT_CC_VRRC ||
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MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
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MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
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MI->getOpcode() == PPC::SELECT_CC_VSRC ||
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MI->getOpcode() == PPC::SELECT_I4 ||
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MI->getOpcode() == PPC::SELECT_I8 ||
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@ -8393,6 +8403,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MI->getOpcode() == PPC::SELECT_QBRC ||
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MI->getOpcode() == PPC::SELECT_VRRC ||
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MI->getOpcode() == PPC::SELECT_VSFRC ||
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MI->getOpcode() == PPC::SELECT_VSSRC ||
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MI->getOpcode() == PPC::SELECT_VSRC) {
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// The incoming instruction knows the destination vreg to set, the
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// condition code register to branch on, the true/false values to
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@ -8429,6 +8440,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MI->getOpcode() == PPC::SELECT_QBRC ||
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MI->getOpcode() == PPC::SELECT_VRRC ||
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MI->getOpcode() == PPC::SELECT_VSFRC ||
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MI->getOpcode() == PPC::SELECT_VSSRC ||
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MI->getOpcode() == PPC::SELECT_VSRC) {
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BuildMI(BB, dl, TII->get(PPC::BC))
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.addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
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@ -10648,7 +10660,10 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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Constraint == "wf") {
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return std::make_pair(0U, &PPC::VSRCRegClass);
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} else if (Constraint == "ws") {
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return std::make_pair(0U, &PPC::VSFRCRegClass);
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if (VT == MVT::f32)
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return std::make_pair(0U, &PPC::VSSRCRegClass);
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else
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return std::make_pair(0U, &PPC::VSFRCRegClass);
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}
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std::pair<unsigned, const TargetRegisterClass *> R =
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@ -815,7 +815,8 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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// copies are generated, they are close enough to some use that the
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// lower-latency form is preferable.
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Opc = PPC::XXLOR;
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else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg))
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else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
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PPC::VSSRCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::XXLORf;
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else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::QVFMR;
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@ -900,6 +901,12 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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getKillRegState(isKill)),
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FrameIdx));
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NonRI = true;
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} else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
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.addReg(SrcReg,
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getKillRegState(isKill)),
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FrameIdx));
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NonRI = true;
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} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
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assert(Subtarget.isDarwin() &&
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"VRSAVE only needs spill/restore on Darwin");
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@ -1013,6 +1020,10 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
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FrameIdx));
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NonRI = true;
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} else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
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FrameIdx));
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NonRI = true;
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} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
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assert(Subtarget.isDarwin() &&
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"VRSAVE only needs spill/restore on Darwin");
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@ -40,6 +40,13 @@ def vsfrc : RegisterOperand<VSFRC> {
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let ParserMatchClass = PPCRegVSFRCAsmOperand;
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}
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def PPCRegVSSRCAsmOperand : AsmOperandClass {
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let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber";
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}
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def vssrc : RegisterOperand<VSSRC> {
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let ParserMatchClass = PPCRegVSSRCAsmOperand;
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}
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// Little-endian-specific nodes.
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def SDT_PPClxvd2x : SDTypeProfile<1, 1, [
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SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
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@ -103,7 +110,7 @@ let Uses = [RM] in {
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvw4x $XT, $src", IIC_LdStLFD,
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[(set v4i32:$XT, (int_ppc_vsx_lxvw4x xoaddr:$src))]>;
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}
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} // mayLoad
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// Store indexed instructions
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let mayStore = 1 in {
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@ -121,7 +128,8 @@ let Uses = [RM] in {
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(outs), (ins vsrc:$XT, memrr:$dst),
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"stxvw4x $XT, $dst", IIC_LdStSTFD,
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[(store v4i32:$XT, xoaddr:$dst)]>;
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}
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} // mayStore
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// Add/Mul Instructions
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let isCommutable = 1 in {
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@ -791,6 +799,15 @@ let usesCustomInserter = 1, // Expanded after instruction selection.
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"#SELECT_VSFRC",
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[(set f64:$dst,
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(select i1:$cond, f64:$T, f64:$F))]>;
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def SELECT_CC_VSSRC: Pseudo<(outs f4rc:$dst),
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(ins crrc:$cond, f4rc:$T, f4rc:$F,
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i32imm:$BROPC), "#SELECT_CC_VSSRC",
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[]>;
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def SELECT_VSSRC: Pseudo<(outs f4rc:$dst),
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(ins crbitrc:$cond, f4rc:$T, f4rc:$F),
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"#SELECT_VSSRC",
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[(set f32:$dst,
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(select i1:$cond, f32:$T, f32:$F))]>;
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} // usesCustomInserter
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} // AddedComplexity
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@ -987,7 +1004,45 @@ def XXLORC : XX3Form<60, 170,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xxlorc $XT, $XA, $XB", IIC_VecGeneral,
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[(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
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} // AddedComplexity = 500
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// VSX scalar loads introduced in ISA 2.07
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let mayLoad = 1 in {
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def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins memrr:$src),
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"lxsspx $XT, $src", IIC_LdStLFD,
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[(set f32:$XT, (load xoaddr:$src))]>;
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def LXSIWAX : XX1Form<31, 76, (outs vsfrc:$XT), (ins memrr:$src),
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"lxsiwax $XT, $src", IIC_LdStLFD,
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[(set f64:$XT, (PPClfiwax xoaddr:$src))]>;
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def LXSIWZX : XX1Form<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
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"lxsiwzx $XT, $src", IIC_LdStLFD,
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[(set f64:$XT, (PPClfiwzx xoaddr:$src))]>;
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} // mayLoad
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// VSX scalar stores introduced in ISA 2.07
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let mayStore = 1 in {
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def STXSSPX : XX1Form<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
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"stxsspx $XT, $dst", IIC_LdStSTFD,
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[(store f32:$XT, xoaddr:$dst)]>;
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def STXSIWX : XX1Form<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
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"stxsiwx $XT, $dst", IIC_LdStSTFD,
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[(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
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} // mayStore
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def : Pat<(f64 (extloadf32 xoaddr:$src)),
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(COPY_TO_REGCLASS (LXSSPX xoaddr:$src), VSFRC)>;
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def : Pat<(f64 (fextend f32:$src)),
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(COPY_TO_REGCLASS $src, VSFRC)>;
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def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
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(SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
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def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
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(SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;
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def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
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(SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
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(SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
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(SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
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(SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
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} // AddedComplexity = 400
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} // HasP8Vector
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let Predicates = [HasDirectMove, HasVSX] in {
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@ -282,6 +282,7 @@ unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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return 32 - DefaultSafety;
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case PPC::VSRCRegClassID:
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case PPC::VSFRCRegClassID:
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case PPC::VSSRCRegClassID:
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return 64 - DefaultSafety;
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case PPC::CRRCRegClassID:
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return 8 - DefaultSafety;
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@ -300,6 +301,8 @@ PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
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return &PPC::VSFRCRegClass;
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else if (RC == &PPC::VRRCRegClass)
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return &PPC::VSRCRegClass;
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else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
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return &PPC::VSSRCRegClass;
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}
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return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
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@ -316,6 +316,9 @@ def VFRC : RegisterClass<"PPC", [f64], 64,
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VF22, VF21, VF20)>;
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def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>;
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||||
|
||||
// Register class for single precision scalars in VSX registers
|
||||
def VSSRC : RegisterClass<"PPC", [f32], 32, (add VSFRC)>;
|
||||
|
||||
// For QPX
|
||||
def QFRC : RegisterClass<"PPC", [v4f64], 256, (add (sequence "QF%u", 0, 13),
|
||||
(sequence "QF%u", 31, 14))>;
|
||||
|
||||
@ -42,7 +42,8 @@ entry:
|
||||
ret float %x
|
||||
}
|
||||
; CHECK: @callee2
|
||||
; CHECK: lfs {{[0-9]+}}, 136(1)
|
||||
; CHECK: addi [[TOCREG:[0-9]+]], 1, 136
|
||||
; CHECK: lxsspx {{[0-9]+}}, {{[0-9]+}}, [[TOCREG]]
|
||||
; CHECK: blr
|
||||
|
||||
define void @caller2() {
|
||||
@ -52,7 +53,8 @@ entry:
|
||||
ret void
|
||||
}
|
||||
; CHECK: @caller2
|
||||
; CHECK: stfs {{[0-9]+}}, 136(1)
|
||||
; CHECK: li [[TOCOFF:[0-9]+]], 136
|
||||
; CHECK: stxsspx {{[0-9]+}}, 1, [[TOCOFF]]
|
||||
; CHECK: bl test2
|
||||
|
||||
declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float)
|
||||
|
||||
139
test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
Normal file
139
test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
Normal file
@ -0,0 +1,139 @@
|
||||
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
|
||||
|
||||
@d = common global double 0.000000e+00, align 8
|
||||
@f = common global float 0.000000e+00, align 4
|
||||
@i = common global i32 0, align 4
|
||||
@ui = common global i32 0, align 4
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dblToInt() #0 {
|
||||
entry:
|
||||
%ii = alloca i32, align 4
|
||||
%0 = load double, double* @d, align 8
|
||||
%conv = fptosi double %0 to i32
|
||||
store volatile i32 %conv, i32* %ii, align 4
|
||||
ret void
|
||||
; CHECK-LABEL: @dblToInt
|
||||
; CHECK: xscvdpsxws [[REGCONV1:[0-9]+]],
|
||||
; CHECK: stxsiwx [[REGCONV1]],
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @fltToInt() #0 {
|
||||
entry:
|
||||
%ii = alloca i32, align 4
|
||||
%0 = load float, float* @f, align 4
|
||||
%conv = fptosi float %0 to i32
|
||||
store volatile i32 %conv, i32* %ii, align 4
|
||||
ret void
|
||||
; CHECK-LABEL: @fltToInt
|
||||
; CHECK: xscvdpsxws [[REGCONV2:[0-9]+]],
|
||||
; CHECK: stxsiwx [[REGCONV2]],
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @intToDbl() #0 {
|
||||
entry:
|
||||
%dd = alloca double, align 8
|
||||
%0 = load i32, i32* @i, align 4
|
||||
%conv = sitofp i32 %0 to double
|
||||
store volatile double %conv, double* %dd, align 8
|
||||
ret void
|
||||
; CHECK-LABEL: @intToDbl
|
||||
; CHECK: lxsiwax [[REGLD1:[0-9]+]],
|
||||
; CHECK: xscvsxddp {{[0-9]+}}, [[REGLD1]]
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @intToFlt() #0 {
|
||||
entry:
|
||||
%ff = alloca float, align 4
|
||||
%0 = load i32, i32* @i, align 4
|
||||
%conv = sitofp i32 %0 to float
|
||||
store volatile float %conv, float* %ff, align 4
|
||||
ret void
|
||||
; CHECK-LABEL: @intToFlt
|
||||
; CHECK: lxsiwax [[REGLD2:[0-9]+]],
|
||||
; FIXME: the below will change when the VSX form is implemented
|
||||
; CHECK: fcfids {{[0-9]}}, [[REGLD2]]
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dblToUInt() #0 {
|
||||
entry:
|
||||
%uiui = alloca i32, align 4
|
||||
%0 = load double, double* @d, align 8
|
||||
%conv = fptoui double %0 to i32
|
||||
store volatile i32 %conv, i32* %uiui, align 4
|
||||
ret void
|
||||
; CHECK-LABEL: @dblToUInt
|
||||
; CHECK: xscvdpuxws [[REGCONV3:[0-9]+]],
|
||||
; CHECK: stxsiwx [[REGCONV3]],
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @fltToUInt() #0 {
|
||||
entry:
|
||||
%uiui = alloca i32, align 4
|
||||
%0 = load float, float* @f, align 4
|
||||
%conv = fptoui float %0 to i32
|
||||
store volatile i32 %conv, i32* %uiui, align 4
|
||||
ret void
|
||||
; CHECK-LABEL: @fltToUInt
|
||||
; CHECK: xscvdpuxws [[REGCONV4:[0-9]+]],
|
||||
; CHECK: stxsiwx [[REGCONV4]],
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @uIntToDbl() #0 {
|
||||
entry:
|
||||
%dd = alloca double, align 8
|
||||
%0 = load i32, i32* @ui, align 4
|
||||
%conv = uitofp i32 %0 to double
|
||||
store volatile double %conv, double* %dd, align 8
|
||||
ret void
|
||||
; CHECK-LABEL: @uIntToDbl
|
||||
; CHECK: lxsiwzx [[REGLD3:[0-9]+]],
|
||||
; CHECK: xscvuxddp {{[0-9]+}}, [[REGLD3]]
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @uIntToFlt() #0 {
|
||||
entry:
|
||||
%ff = alloca float, align 4
|
||||
%0 = load i32, i32* @ui, align 4
|
||||
%conv = uitofp i32 %0 to float
|
||||
store volatile float %conv, float* %ff, align 4
|
||||
ret void
|
||||
; CHECK-LABEL: @uIntToFlt
|
||||
; CHECK: lxsiwzx [[REGLD4:[0-9]+]],
|
||||
; FIXME: the below will change when the VSX form is implemented
|
||||
; CHECK: fcfidus {{[0-9]+}}, [[REGLD4]]
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @dblToFloat() #0 {
|
||||
entry:
|
||||
%ff = alloca float, align 4
|
||||
%0 = load double, double* @d, align 8
|
||||
%conv = fptrunc double %0 to float
|
||||
store volatile float %conv, float* %ff, align 4
|
||||
ret void
|
||||
; CHECK-LABEL: @dblToFloat
|
||||
; CHECK: lxsdx [[REGLD5:[0-9]+]],
|
||||
; CHECK: stxsspx [[REGLD5]],
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @floatToDbl() #0 {
|
||||
entry:
|
||||
%dd = alloca double, align 8
|
||||
%0 = load float, float* @f, align 4
|
||||
%conv = fpext float %0 to double
|
||||
store volatile double %conv, double* %dd, align 8
|
||||
ret void
|
||||
; CHECK-LABEL: @floatToDbl
|
||||
; CHECK: lxsspx [[REGLD5:[0-9]+]],
|
||||
; CHECK: stxsdx [[REGLD5]],
|
||||
}
|
||||
@ -3,6 +3,15 @@
|
||||
# CHECK: lxsdx 7, 5, 31
|
||||
0x7c 0xe5 0xfc 0x98
|
||||
|
||||
# CHECK: lxsiwax 7, 5, 31
|
||||
0x7c 0xe5 0xf8 0x98
|
||||
|
||||
# CHECK: lxsiwzx 7, 5, 31
|
||||
0x7c 0xe5 0xf8 0x18
|
||||
|
||||
# CHECK: lxsspx 7, 5, 31
|
||||
0x7c 0xe5 0xfc 0x18
|
||||
|
||||
# CHECK: lxvd2x 7, 5, 31
|
||||
0x7c 0xe5 0xfe 0x98
|
||||
|
||||
@ -15,6 +24,12 @@
|
||||
# CHECK: stxsdx 8, 5, 31
|
||||
0x7d 0x05 0xfd 0x98
|
||||
|
||||
# CHECK: stxsiwx 8, 5, 31
|
||||
0x7d 0x05 0xf9 0x18
|
||||
|
||||
# CHECK: stxsspx 8, 5, 31
|
||||
0x7d 0x05 0xfd 0x18
|
||||
|
||||
# CHECK: stxvd2x 8, 5, 31
|
||||
0x7d 0x05 0xff 0x98
|
||||
|
||||
|
||||
@ -5,26 +5,41 @@
|
||||
# CHECK-LE: xxswapd 7, 63 # encoding: [0x56,0xfa,0xff,0xf0]
|
||||
xxswapd %vs7, %vs63
|
||||
|
||||
# CHECK-BE: lxsdx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x99]
|
||||
# CHECK-LE: lxsdx 39, 5, 31 # encoding: [0x99,0xfc,0xe5,0x7c]
|
||||
# CHECK-BE: lxsdx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x99]
|
||||
# CHECK-LE: lxsdx 39, 5, 31 # encoding: [0x99,0xfc,0xe5,0x7c]
|
||||
lxsdx 39, 5, 31
|
||||
# CHECK-BE: lxvd2x 39, 5, 31 # encoding: [0x7c,0xe5,0xfe,0x99]
|
||||
# CHECK-LE: lxvd2x 39, 5, 31 # encoding: [0x99,0xfe,0xe5,0x7c]
|
||||
# CHECK-BE: lxsiwax 39, 5, 31 # encoding: [0x7c,0xe5,0xf8,0x99]
|
||||
# CHECK-LE: lxsiwax 39, 5, 31 # encoding: [0x99,0xf8,0xe5,0x7c]
|
||||
lxsiwax 39, 5, 31
|
||||
# CHECK-BE: lxsiwzx 39, 5, 31 # encoding: [0x7c,0xe5,0xf8,0x19]
|
||||
# CHECK-LE: lxsiwzx 39, 5, 31 # encoding: [0x19,0xf8,0xe5,0x7c]
|
||||
lxsiwzx 39, 5, 31
|
||||
# CHECK-BE: lxsspx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x19]
|
||||
# CHECK-LE: lxsspx 39, 5, 31 # encoding: [0x19,0xfc,0xe5,0x7c]
|
||||
lxsspx 39, 5, 31
|
||||
# CHECK-BE: lxvd2x 39, 5, 31 # encoding: [0x7c,0xe5,0xfe,0x99]
|
||||
# CHECK-LE: lxvd2x 39, 5, 31 # encoding: [0x99,0xfe,0xe5,0x7c]
|
||||
lxvd2x 39, 5, 31
|
||||
# CHECK-BE: lxvdsx 39, 5, 31 # encoding: [0x7c,0xe5,0xfa,0x99]
|
||||
# CHECK-LE: lxvdsx 39, 5, 31 # encoding: [0x99,0xfa,0xe5,0x7c]
|
||||
# CHECK-BE: lxvdsx 39, 5, 31 # encoding: [0x7c,0xe5,0xfa,0x99]
|
||||
# CHECK-LE: lxvdsx 39, 5, 31 # encoding: [0x99,0xfa,0xe5,0x7c]
|
||||
lxvdsx 39, 5, 31
|
||||
# CHECK-BE: lxvw4x 39, 5, 31 # encoding: [0x7c,0xe5,0xfe,0x19]
|
||||
# CHECK-LE: lxvw4x 39, 5, 31 # encoding: [0x19,0xfe,0xe5,0x7c]
|
||||
# CHECK-BE: lxvw4x 39, 5, 31 # encoding: [0x7c,0xe5,0xfe,0x19]
|
||||
# CHECK-LE: lxvw4x 39, 5, 31 # encoding: [0x19,0xfe,0xe5,0x7c]
|
||||
lxvw4x 39, 5, 31
|
||||
# CHECK-BE: stxsdx 40, 5, 31 # encoding: [0x7d,0x05,0xfd,0x99]
|
||||
# CHECK-LE: stxsdx 40, 5, 31 # encoding: [0x99,0xfd,0x05,0x7d]
|
||||
# CHECK-BE: stxsdx 40, 5, 31 # encoding: [0x7d,0x05,0xfd,0x99]
|
||||
# CHECK-LE: stxsdx 40, 5, 31 # encoding: [0x99,0xfd,0x05,0x7d]
|
||||
stxsdx 40, 5, 31
|
||||
# CHECK-BE: stxvd2x 40, 5, 31 # encoding: [0x7d,0x05,0xff,0x99]
|
||||
# CHECK-LE: stxvd2x 40, 5, 31 # encoding: [0x99,0xff,0x05,0x7d]
|
||||
# CHECK-BE: stxsiwx 40, 5, 31 # encoding: [0x7d,0x05,0xf9,0x19]
|
||||
# CHECK-LE: stxsiwx 40, 5, 31 # encoding: [0x19,0xf9,0x05,0x7d]
|
||||
stxsiwx 40, 5, 31
|
||||
# CHECK-BE: stxsspx 40, 5, 31 # encoding: [0x7d,0x05,0xfd,0x19]
|
||||
# CHECK-LE: stxsspx 40, 5, 31 # encoding: [0x19,0xfd,0x05,0x7d]
|
||||
stxsspx 40, 5, 31
|
||||
# CHECK-BE: stxvd2x 40, 5, 31 # encoding: [0x7d,0x05,0xff,0x99]
|
||||
# CHECK-LE: stxvd2x 40, 5, 31 # encoding: [0x99,0xff,0x05,0x7d]
|
||||
stxvd2x 40, 5, 31
|
||||
# CHECK-BE: stxvw4x 40, 5, 31 # encoding: [0x7d,0x05,0xff,0x19]
|
||||
# CHECK-LE: stxvw4x 40, 5, 31 # encoding: [0x19,0xff,0x05,0x7d]
|
||||
# CHECK-BE: stxvw4x 40, 5, 31 # encoding: [0x7d,0x05,0xff,0x19]
|
||||
# CHECK-LE: stxvw4x 40, 5, 31 # encoding: [0x19,0xff,0x05,0x7d]
|
||||
stxvw4x 40, 5, 31
|
||||
# CHECK-BE: xsabsdp 7, 27 # encoding: [0xf0,0xe0,0xdd,0x64]
|
||||
# CHECK-LE: xsabsdp 7, 27 # encoding: [0x64,0xdd,0xe0,0xf0]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user