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R600/SI: Refactor AMDGPUAsmPrinter::EmitProgramInfoSI()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223144 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -358,19 +358,21 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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ProgInfo.CodeLen = CodeSize;
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}
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static unsigned getRsrcReg(unsigned ShaderType) {
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switch (ShaderType) {
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default: // Fall through
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case ShaderType::COMPUTE: return R_00B848_COMPUTE_PGM_RSRC1;
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case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
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case ShaderType::PIXEL: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
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case ShaderType::VERTEX: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
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}
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}
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void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
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const SIProgramInfo &KernelInfo) {
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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unsigned RsrcReg;
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switch (MFI->getShaderType()) {
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default: // Fall through
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case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
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case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
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case ShaderType::PIXEL: RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
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case ShaderType::VERTEX: RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
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}
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unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
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unsigned LDSAlignShift;
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if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
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