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Fix the post-RA instruction scheduler to handle instructions referenced by

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more than one dbg_value instruction. rdar://7759363


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-05-19 22:57:06 +00:00
parent e163168aab
commit 309d20c89c
2 changed files with 8 additions and 21 deletions
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23
include/llvm/CodeGen/ScheduleDAG.h
View File

@ -225,7 +225,6 @@ namespace llvm {
private:
SDNode *Node; // Representative node.
MachineInstr *Instr; // Alternatively, a MachineInstr.
MachineInstr *DbgInstr; // A dbg_value referencing this.
public:
SUnit *OrigNode; // If not this, the node from which
// this node was cloned.
@ -256,6 +255,8 @@ namespace llvm {
bool isScheduled : 1; // True once scheduled.
bool isScheduleHigh : 1; // True if preferable to schedule high.
bool isCloned : 1; // True if this node has been cloned.
SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this.
private:
bool isDepthCurrent : 1; // True if Depth is current.
bool isHeightCurrent : 1; // True if Height is current.
@ -268,7 +269,7 @@ namespace llvm {
/// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
/// an SDNode and any nodes flagged to it.
SUnit(SDNode *node, unsigned nodenum)
: Node(node), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(nodenum),
: Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
hasPhysRegDefs(false), hasPhysRegClobbers(false),
@ -280,7 +281,7 @@ namespace llvm {
/// SUnit - Construct an SUnit for post-regalloc scheduling to represent
/// a MachineInstr.
SUnit(MachineInstr *instr, unsigned nodenum)
: Node(0), Instr(instr), DbgInstr(0), OrigNode(0), NodeNum(nodenum),
: Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
hasPhysRegDefs(false), hasPhysRegClobbers(false),
@ -291,7 +292,7 @@ namespace llvm {
/// SUnit - Construct a placeholder SUnit.
SUnit()
: Node(0), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(~0u),
: Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
hasPhysRegDefs(false), hasPhysRegClobbers(false),
@ -328,20 +329,6 @@ namespace llvm {
return Instr;
}
/// setDbgInstr - Assign the debug instruction for the SUnit.
/// This may be used during post-regalloc scheduling.
void setDbgInstr(MachineInstr *MI) {
assert(!Node && "Setting debug MachineInstr of SUnit with SDNode!");
DbgInstr = MI;
}
/// getDbgInstr - Return the debug MachineInstr for this SUnit.
/// This may be used during post-regalloc scheduling.
MachineInstr *getDbgInstr() const {
assert(!Node && "Reading debug MachineInstr of SUnit with SDNode!");
return DbgInstr;
}
/// addPred - This adds the specified edge as a pred of the current node if
/// not already. It also adds the current node as a successor of the
/// specified node.

6
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -210,7 +210,7 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
if (MO.isDef() && DanglingDebugValue[Reg].first!=0) {
SU->setDbgInstr(DanglingDebugValue[Reg].first);
SU->DbgInstrList.push_back(DanglingDebugValue[Reg].first);
DbgValueVec[DanglingDebugValue[Reg].second] = 0;
DanglingDebugValue[Reg] = std::make_pair((MachineInstr*)0, 0);
}
@ -599,8 +599,8 @@ MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
}
BB->insert(InsertPos, SU->getInstr());
if (SU->getDbgInstr())
BB->insert(InsertPos, SU->getDbgInstr());
for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i)
BB->insert(InsertPos, SU->DbgInstrList[i]);
}
// Update the Begin iterator, as the first instruction in the block