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Eliminate bool, boolreg and boolconst nonterminals, and just use
reg and Constant instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3441 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -168,7 +168,8 @@ ChooseBccInstruction(const InstructionNode* instrNode,
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bool& isFPBranch)
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{
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InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
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BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
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assert(setCCNode->getOpLabel() == SetCCOp);
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BinaryOperator* setCCInstr =cast<BinaryOperator>(setCCNode->getInstruction());
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const Type* setCCType = setCCInstr->getOperand(0)->getType();
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isFPBranch = setCCType->isFloatingPoint(); // Return value: don't delete!
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@ -1218,7 +1219,6 @@ ThisIsAChainRule(int eruleno)
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switch(eruleno)
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{
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case 111: // stmt: reg
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case 113: // stmt: bool
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case 123:
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case 124:
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case 125:
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@ -1237,9 +1237,10 @@ ThisIsAChainRule(int eruleno)
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case 242:
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case 243:
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case 244:
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case 245:
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case 321:
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return true; break;
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default:
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return false; break;
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}
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@ -1394,18 +1395,16 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// ELSE FALL THROUGH
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}
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case 6: // stmt: BrCond(bool)
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{ // bool => boolean was computed with some boolean operator
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// (SetCC, Not, ...). We need to check whether the type was a FP,
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// signed int or unsigned int, and check the branching condition in
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// order to choose the branch to use.
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case 6: // stmt: BrCond(setCC)
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{ // bool => boolean was computed with SetCC.
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// The branch to use depends on whether it is FP, signed, or unsigned.
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// If it is an integer CC, we also need to find the unique
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// TmpInstruction representing that CC.
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//
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BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
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bool isFPBranch;
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M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
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Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
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brInst->getParent()->getParent(),
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isFPBranch? Type::FloatTy : Type::IntTy);
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@ -1414,16 +1413,16 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
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brInst->getSuccessor(0));
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mvec.push_back(M);
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// delay slot
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mvec.push_back(new MachineInstr(NOP));
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// false branch
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M = new MachineInstr(BA);
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M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
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brInst->getSuccessor(1));
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mvec.push_back(M);
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// delay slot
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mvec.push_back(new MachineInstr(NOP));
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break;
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@ -1490,7 +1489,6 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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break;
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}
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case 322: // reg: ToBoolTy(bool):
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case 22: // reg: ToBoolTy(reg):
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{
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const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
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@ -1973,10 +1971,6 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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break;
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}
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case 43: // boolreg: VReg
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case 44: // boolreg: Constant
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break;
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case 51: // reg: Load(reg)
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case 52: // reg: Load(ptrreg)
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case 53: // reg: LoadIdx(reg,reg)
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